AL
Physical Design Engineer
Accepting applicationsAstera Labs · San Jose, CA
Full-Time Mid_senior ASICCadenceDFTPerlRTL
Posted
21 Apr
Category
Design
Experience
Mid_senior
Country
United States
Here at Astera Labs we are in need of 3 Physical design Engineers with 8 to 10 years of experience.
As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person.
Basic Qualifications:
Strong academic and technical background in electrical engineering. A bachelor's degree in EE / Computer Science is required, and a master's degree is preferred.
≥10 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
Entrepreneurial, open-minded behavior and a can-do attitude. Think and act fast with the customer in mind!
Required Experience:
Proven expertise in developing/maintaining timing constraints, timing signoff methodology, and timing closure at the block and full-chip level.
Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
Experience with Cadence and/or Synopsys physical design tools/flows.
Familiarity and working knowledge of System Verilog/Verilog.
Experience with DFT tools and techniques.
Experience in working with IP vendors for both RTL and hard-macro blocks.
Good scripting skills in tcl, python, or Perl.
Preferred Experience:
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
Familiarity with DFT test coverage and debug.
Familiarity with ECO methodologies and tools.
If this sounds like you and you're interested, please apply and if not feel free to forward to others you might know.
Show more Show less
As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person.
Basic Qualifications:
Strong academic and technical background in electrical engineering. A bachelor's degree in EE / Computer Science is required, and a master's degree is preferred.
≥10 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
Entrepreneurial, open-minded behavior and a can-do attitude. Think and act fast with the customer in mind!
Required Experience:
Proven expertise in developing/maintaining timing constraints, timing signoff methodology, and timing closure at the block and full-chip level.
Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
Experience with Cadence and/or Synopsys physical design tools/flows.
Familiarity and working knowledge of System Verilog/Verilog.
Experience with DFT tools and techniques.
Experience in working with IP vendors for both RTL and hard-macro blocks.
Good scripting skills in tcl, python, or Perl.
Preferred Experience:
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
Familiarity with DFT test coverage and debug.
Familiarity with ECO methodologies and tools.
If this sounds like you and you're interested, please apply and if not feel free to forward to others you might know.
Show more Show less