Physical Design Engineer

● 7+ years of experience in physical design.
● A good grasp of RTL2GDS flow and design tapeouts in 5nm or smaller process tech.
● Experience with Synopsys EDA tools like Fusion Compiler and Primetime. Additional skills the Whole Team Needs (as a collective):
● Experience with custom or regular clock tree synthesis (block or top level) and techniques to reduce clock power.
● Experience with low-power implementation, power gating, multiple voltage rails, and UPF knowledge.
● Experience with PTPX power flow.
rails, and UPF knowledge.
● Experience with PTPX power flow.
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