AC
Physical Design Engineer
Accepting applicationsApetan Consulting LLC · West Menlo Park, CA
Full-Time Senior Synopsys
Posted
4d ago
Category
Design
Experience
Senior
Country
United States
Role: Physical Design Engineer
Location: San Jose, CA
Job Description
Handling the physical design implementation for various partitions using advanced tech, including things like physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, and EMIR. They'll also sort out any design and flow issues related to physical design, figure out solutions, and get things done.
Required Skills
Bachelor s degree in electrical engineering (or similar experience).
7+ years of experience in physical design.
A good grasp of RTL2GDS flow and design tapeouts in 5nm or smaller process tech.
Experience with Synopsys EDA tools like Fusion Compiler and Primetime. Additional skills the Whole Team Needs (as a collective):
Experience with custom or regular clock tree synthesis (block or top level) and techniques to reduce clock power.
Experience with low-power implementation, power gating, multiple voltage rails, and UPF knowledge.
Experience with PTPX power flow.
rails, and UPF knowledge.
Experience with PTPX power flow.
Show more Show less
Location: San Jose, CA
Job Description
Handling the physical design implementation for various partitions using advanced tech, including things like physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, and EMIR. They'll also sort out any design and flow issues related to physical design, figure out solutions, and get things done.
Required Skills
Bachelor s degree in electrical engineering (or similar experience).
7+ years of experience in physical design.
A good grasp of RTL2GDS flow and design tapeouts in 5nm or smaller process tech.
Experience with Synopsys EDA tools like Fusion Compiler and Primetime. Additional skills the Whole Team Needs (as a collective):
Experience with custom or regular clock tree synthesis (block or top level) and techniques to reduce clock power.
Experience with low-power implementation, power gating, multiple voltage rails, and UPF knowledge.
Experience with PTPX power flow.
rails, and UPF knowledge.
Experience with PTPX power flow.
Show more Show less
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