PT
Physical Design Engineer (6 to 15 Yrs)
Accepting applicationsPozibility Technologies Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Entry ASICCadenceDFTFPGAMentor
Estimated market salary
₹12-20 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Design
Experience
Entry
Country
India
Company Description Pozibility Technologies Pvt Ltd is a design services company founded by industry experts with more than 18 years of experience in ASIC design services and embedded software development. The company enables customers with end-to-end IC design, embedded software, software testing, and system design solutions through a motivated team of skilled engineers. Its expertise spans ASIC/SoC architecture design, RTL coding and verification, FPGA design and prototyping, synthesis and STA, formal verification, DFT, physical design, and analog mixed-signal design and layout. Pozibility also provides strong embedded software capabilities from pre-silicon development through boot loaders, device drivers, and hardware abstraction layers. Dedicated testing services help enterprises ensure their products and applications meet quality standards and market expectations.
Role Description This is a full-time, on-site Physical Design Engineer role based in Bengaluru. The engineer will work on ASIC/SoC implementation flows, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Day-to-day responsibilities include collaborating with logic and RTL design teams, performing physical verification, power and area optimization, and ensuring that designs meet performance, reliability, and manufacturability requirements. The role involves working with industry-standard EDA tools, preparing sign-off reports, handling ECOs, and supporting tape-out activities. The engineer will also participate in design reviews, contribute to methodology improvement, and mentor junior team members as needed.
Qualifications
Candidates should possess strong skills in Physical Design, including floorplanning, placement, CTS, routing, timing closure, and power/area optimization.
Candidates should possess skills in Physical Verification, including DRC, LVS, ERC, and familiarity with sign-off flows and tools.
Candidates should possess skills in Logic Design and Circuit Design, with understanding of digital design concepts, timing, power, and signal integrity.
Candidates should possess skills in RTL Design, including interpreting and reviewing RTL, and collaborating effectively with front-end design and verification teams.
6 to 15 years of relevant experience in ASIC/SoC physical design and implementation.
Hands-on experience with leading EDA tools (such as Cadence, Synopsys, or Mentor) and advanced process nodes.
Strong problem-solving abilities, analytical skills, and attention to detail, with the ability to work on complex designs under schedule constraints.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related field, or equivalent practical experience.
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Role Description This is a full-time, on-site Physical Design Engineer role based in Bengaluru. The engineer will work on ASIC/SoC implementation flows, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Day-to-day responsibilities include collaborating with logic and RTL design teams, performing physical verification, power and area optimization, and ensuring that designs meet performance, reliability, and manufacturability requirements. The role involves working with industry-standard EDA tools, preparing sign-off reports, handling ECOs, and supporting tape-out activities. The engineer will also participate in design reviews, contribute to methodology improvement, and mentor junior team members as needed.
Qualifications
Candidates should possess strong skills in Physical Design, including floorplanning, placement, CTS, routing, timing closure, and power/area optimization.
Candidates should possess skills in Physical Verification, including DRC, LVS, ERC, and familiarity with sign-off flows and tools.
Candidates should possess skills in Logic Design and Circuit Design, with understanding of digital design concepts, timing, power, and signal integrity.
Candidates should possess skills in RTL Design, including interpreting and reviewing RTL, and collaborating effectively with front-end design and verification teams.
6 to 15 years of relevant experience in ASIC/SoC physical design and implementation.
Hands-on experience with leading EDA tools (such as Cadence, Synopsys, or Mentor) and advanced process nodes.
Strong problem-solving abilities, analytical skills, and attention to detail, with the ability to work on complex designs under schedule constraints.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related field, or equivalent practical experience.
Show more Show less