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Physical Design Engineer - 5+ Years - Bangalore Location
Accepting applicationsleadIC Design Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Entry ASICCadenceDFTMentorPerl
Estimated market salary
₹12-20 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Design
Experience
Entry
Country
India
Company Description LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise, supporting the complete chip development lifecycle for global semiconductor companies. Founded in 2018, the company has grown into a trusted partner known for deep technical capability, strong ownership, and flexible engagement models. With engineering teams across India and Canada, LeadIC delivers high-quality design services spanning custom layout, analog/mixed-signal, digital design, verification, and physical design. The organization emphasizes a proactive, accountable engineering culture, rigorous quality processes, and scalable offshore development centers. Long-term relationships with leading semiconductor firms reflect LeadIC’s focus on reliable, value-driven technical partnerships that help bring complex silicon products to market.
Role Description This is a full-time, on-site Physical Design Engineer role based in Bengaluru. The engineer will be responsible for end-to-end physical design implementation, including floorplanning, placement, clock tree synthesis, routing, and timing closure for complex digital chips. Daily activities include working on synthesis-to-signoff flows, collaborating with RTL and verification teams, and ensuring designs meet power, performance, and area targets. The role involves running and analyzing physical verification checks, resolving design and layout issues, and optimizing physical implementation for manufacturability and reliability. The engineer will also contribute to methodology improvements, maintain documentation, and support tape-out activities for multiple projects.
Qualifications
Strong expertise in Physical Design, including synthesis, floorplanning, placement, CTS, routing, and timing closure.
Hands-on experience with Physical Verification, including DRC, LVS, and signoff checks using industry-standard tools.
Solid understanding of Logic Design and Circuit Design concepts, including timing, power, and signal integrity fundamentals.
Proficiency in RTL Design, working with RTL teams to debug issues, constrain designs, and enable efficient implementation.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related field.
5+ years of relevant experience in ASIC physical design for advanced technology nodes.
Working knowledge of industry EDA tools (e.g., Cadence, Synopsys, Mentor) and scripting skills in Tcl/Perl/Python for flow automation.
Ability to collaborate in cross-functional teams, communicate clearly, and take ownership of deliverables and schedules.
Experience with STA, DFT, and low-power design techniques is an advantage.
Background in full-chip implementation or tape-out for complex SoCs is highly beneficial.
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Role Description This is a full-time, on-site Physical Design Engineer role based in Bengaluru. The engineer will be responsible for end-to-end physical design implementation, including floorplanning, placement, clock tree synthesis, routing, and timing closure for complex digital chips. Daily activities include working on synthesis-to-signoff flows, collaborating with RTL and verification teams, and ensuring designs meet power, performance, and area targets. The role involves running and analyzing physical verification checks, resolving design and layout issues, and optimizing physical implementation for manufacturability and reliability. The engineer will also contribute to methodology improvements, maintain documentation, and support tape-out activities for multiple projects.
Qualifications
Strong expertise in Physical Design, including synthesis, floorplanning, placement, CTS, routing, and timing closure.
Hands-on experience with Physical Verification, including DRC, LVS, and signoff checks using industry-standard tools.
Solid understanding of Logic Design and Circuit Design concepts, including timing, power, and signal integrity fundamentals.
Proficiency in RTL Design, working with RTL teams to debug issues, constrain designs, and enable efficient implementation.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related field.
5+ years of relevant experience in ASIC physical design for advanced technology nodes.
Working knowledge of industry EDA tools (e.g., Cadence, Synopsys, Mentor) and scripting skills in Tcl/Perl/Python for flow automation.
Ability to collaborate in cross-functional teams, communicate clearly, and take ownership of deliverables and schedules.
Experience with STA, DFT, and low-power design techniques is an advantage.
Background in full-chip implementation or tape-out for complex SoCs is highly beneficial.
Show more Show less