Physical Design

looking for highly motivated Physical Design Engineers with strong expertise in Cadence Innovus and proven experience in TI 28nm, TSMC 28nm, 40nm, 55nm, 65nm, or similar planar (Non-FinFET) technologies.
The ideal candidate should possess hands-on experience in complete Physical Design implementation from Netlist-to-GDSII, including Floorplanning, Power Planning, Placement, CTS, Routing, STA Closure, and Physical Verification. Candidates should have strong ownership in driving design closure for complex SoC/IP/block-level implementations.
Key Responsibilities
Physical Design Implementation
Execute complete Physical Design flow from synthesized netlist to GDSII.
Own block-level or subsystem-level implementation.
Perform:
Floorplanning
Power Planning
Placement Optimization
Clock Tree Synthesis (CTS)
Routing
ECO Closure
Physical Signoff Support
Timing Closure
Drive timing closure across multiple modes and corners.
Resolve:
Setup Violations
Hold Violations
Congestion Issues
Signal Integrity Challenges
Work closely with STA teams for MCMM timing closure.
Physical Verification & Signoff
Support DRC/LVS closure activities.
Analyze and fix physical design issues impacting tapeout.
Collaborate with signoff teams to ensure design readiness.
Power Optimization
Analyze and optimize:
Dynamic Power
Leakage Power
IR Drop
EM Violations
Support power integrity closure activities.
Cross-Functional Collaboration
Work closely with:
RTL Design Teams
DFT Engineers
STA Teams
Verification Engineers
Foundry Teams
Participate in design reviews and implementation planning.
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