U
PHY Layer Engineer
Accepting applicationsUplers · Delhi, India
Full-Time Mid C++FPGAMATLABPythonRF
Estimated market salary
₹12-19 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Design
Experience
Mid
Country
India
Experience: 5.00 + years
Salary: INR 3500000-5500000 / year (based on experience)
Expected Notice Period: 30 Days
Shift: (GMT+05:30) Asia/Kolkata (IST)
Opportunity Type: Office ()
Placement Type: Full Time Permanent position(Payroll and Compliance to be managed by: VL)
(*Note: This is a requirement for one of Uplers' client - VL)
What do you need for this opportunity?
Must have skills required:
VHDL, MATLAB, modulation, Python, Digital signal processing, physical layer, Simulation Exposure, Lifi, RTL
VL is Looking for:
Role: PHY Layer Engineer
Wireless & Optical Wireless Communications
Signal Processing
FPGA
Function: Research & Development — Optical Wireless PHY
Education: M.Tech / M.S. / Ph.D. — ECE, EE, Signal Processing
Experience: 5–8 years
PhD counts as experience
Location: Delhi, On-site
Velmenni is a leading Optical Wireless Communication (OWC) company developing LiFi and Free-Space Optical (FSO) technologies for next-generation high-speed wireless networks. We combine communication theory, signal processing, FPGA acceleration, and photonics to build real-world optical communication systems. Our team works across the full innovation cycle—from research and simulation to hardware prototyping and deployment—creating technologies that complement and extend traditional RF-based wireless networks.
This is an R&D position. You will own the design, development, and experimental validation of physical layer algorithms for LiFi and Free Space Optical (FSO) communication systems — from theoretical formulation and simulation through to FPGA prototyping. Publishing and prototyping are both expected.
Responsibilities
Design and develop PHY algorithms for LiFi and FSO — modulation (OOK, PPM, DCO-OFDM, ACO-OFDM), channel coding (LDPC, Polar, RS), and synchronisation
Model and simulate optical wireless channels: atmospheric turbulence, pointing errors, IM/DD receiver noise, ambient light interference, and LED/laser non-linearities
Build end-to-end link-level simulation chains in MATLAB or Python and evaluate BER, throughput, and spectral efficiency under realistic conditions
Implement validated algorithms on FPGA — translate fixed-point models into RTL or HLS; own algorithm correctness through hardware validation
Write bit-exact C/C++ reference models to support hardware verification
Track and engage with relevant standards: IEEE 802.11bb (LiFi), ITU-T FSO, and adjacent wireless standards
Required
M.Tech, M.S., or Ph.D. in ECE, Electrical Engineering, Signal Processing, or a related field — thesis or research in optical wireless, VLC, or wireless communications is a strong indicator
Strong fundamentals in digital communications: modulation, channel coding, detection, estimation, and synchronisation
Hands-on experience building PHY simulations from scratch in MATLAB or Python — not just toolboxes
Solid understanding of OFDM: multipath channels, cyclic prefix, pilot design, and channel estimation
Fixed-point thinking — ability to design algorithms aware of hardware quantisation and implementation cost
FPGA awareness: understand LUT/DSP/BRAM trade-offs, pipelining, and timing well enough to make
hardware-friendly algorithm decisions
Familiarity with VHDL or Verilog to write or review RTL for PHY blocks
Exposure to AMD/Xilinx Vivado — simulation, synthesis, and reading timing and resource reports
Working knowledge of at least one wireless or optical wireless standard; ability to read and implement from spec documents
Preferred
Experience with 3Gpp, IEEE 802.11bb (LiFi), or ITU FSO link specifications
Optical channel modelling: log-normal turbulence, Gamma-Gamma distribution, pointing error statistics
LED non-linearity, predistortion, and flicker mitigation for VLC systems
Optical MIMO, spatial diversity techniques, and APD / PIN photodetector front-end modelling
Cellular or 5G NR PHY background — OFDM, LDPC, channel coding chain
SDR platforms: Ettus USRP and GNU Radio for over-the-air prototyping
Linux environment and Python / Bash scripting for toolchain automation
Vitis HLS or OpenCL-based FPGA acceleration flows
Publications in IEEE Photonics, IEEE Communications Letters, JOCN, or equivalent venues
Research Profile
We are open to two archetypes:
M.Tech or PhD with thesis in VLC, OWC, optical OFDM, or wireless channel modelling — research output matters more than years of industry experience
Wireless PHY engineer from industry looking to move into R&D — trainable on the optical wireless domain if the PHY and FPGA fundamentals are strong
Interview Process :
First round: Head of Product Development, R&D
Final round: Deepak (CEO)
If possible, a third round might happen
How to apply for this opportunity?
Step 1: Click On Apply! And Register or Login on our portal.
Step 2: Complete the Screening Form & Upload updated Resume
Step 3: Increase your chances to get shortlisted & meet the client for the Interview!
About Uplers:
Our goal is to make hiring reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant contractual onsite opportunities and progress in their career. We will support any grievances or challenges you may face during the engagement.
(Note: There are many more opportunities apart from this on the portal. Depending on the assessments you clear, you can apply for them as well).
So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!
Show more Show less
Salary: INR 3500000-5500000 / year (based on experience)
Expected Notice Period: 30 Days
Shift: (GMT+05:30) Asia/Kolkata (IST)
Opportunity Type: Office ()
Placement Type: Full Time Permanent position(Payroll and Compliance to be managed by: VL)
(*Note: This is a requirement for one of Uplers' client - VL)
What do you need for this opportunity?
Must have skills required:
VHDL, MATLAB, modulation, Python, Digital signal processing, physical layer, Simulation Exposure, Lifi, RTL
VL is Looking for:
Role: PHY Layer Engineer
Wireless & Optical Wireless Communications
Signal Processing
FPGA
Function: Research & Development — Optical Wireless PHY
Education: M.Tech / M.S. / Ph.D. — ECE, EE, Signal Processing
Experience: 5–8 years
PhD counts as experience
Location: Delhi, On-site
Velmenni is a leading Optical Wireless Communication (OWC) company developing LiFi and Free-Space Optical (FSO) technologies for next-generation high-speed wireless networks. We combine communication theory, signal processing, FPGA acceleration, and photonics to build real-world optical communication systems. Our team works across the full innovation cycle—from research and simulation to hardware prototyping and deployment—creating technologies that complement and extend traditional RF-based wireless networks.
This is an R&D position. You will own the design, development, and experimental validation of physical layer algorithms for LiFi and Free Space Optical (FSO) communication systems — from theoretical formulation and simulation through to FPGA prototyping. Publishing and prototyping are both expected.
Responsibilities
Design and develop PHY algorithms for LiFi and FSO — modulation (OOK, PPM, DCO-OFDM, ACO-OFDM), channel coding (LDPC, Polar, RS), and synchronisation
Model and simulate optical wireless channels: atmospheric turbulence, pointing errors, IM/DD receiver noise, ambient light interference, and LED/laser non-linearities
Build end-to-end link-level simulation chains in MATLAB or Python and evaluate BER, throughput, and spectral efficiency under realistic conditions
Implement validated algorithms on FPGA — translate fixed-point models into RTL or HLS; own algorithm correctness through hardware validation
Write bit-exact C/C++ reference models to support hardware verification
Track and engage with relevant standards: IEEE 802.11bb (LiFi), ITU-T FSO, and adjacent wireless standards
Required
M.Tech, M.S., or Ph.D. in ECE, Electrical Engineering, Signal Processing, or a related field — thesis or research in optical wireless, VLC, or wireless communications is a strong indicator
Strong fundamentals in digital communications: modulation, channel coding, detection, estimation, and synchronisation
Hands-on experience building PHY simulations from scratch in MATLAB or Python — not just toolboxes
Solid understanding of OFDM: multipath channels, cyclic prefix, pilot design, and channel estimation
Fixed-point thinking — ability to design algorithms aware of hardware quantisation and implementation cost
FPGA awareness: understand LUT/DSP/BRAM trade-offs, pipelining, and timing well enough to make
hardware-friendly algorithm decisions
Familiarity with VHDL or Verilog to write or review RTL for PHY blocks
Exposure to AMD/Xilinx Vivado — simulation, synthesis, and reading timing and resource reports
Working knowledge of at least one wireless or optical wireless standard; ability to read and implement from spec documents
Preferred
Experience with 3Gpp, IEEE 802.11bb (LiFi), or ITU FSO link specifications
Optical channel modelling: log-normal turbulence, Gamma-Gamma distribution, pointing error statistics
LED non-linearity, predistortion, and flicker mitigation for VLC systems
Optical MIMO, spatial diversity techniques, and APD / PIN photodetector front-end modelling
Cellular or 5G NR PHY background — OFDM, LDPC, channel coding chain
SDR platforms: Ettus USRP and GNU Radio for over-the-air prototyping
Linux environment and Python / Bash scripting for toolchain automation
Vitis HLS or OpenCL-based FPGA acceleration flows
Publications in IEEE Photonics, IEEE Communications Letters, JOCN, or equivalent venues
Research Profile
We are open to two archetypes:
M.Tech or PhD with thesis in VLC, OWC, optical OFDM, or wireless channel modelling — research output matters more than years of industry experience
Wireless PHY engineer from industry looking to move into R&D — trainable on the optical wireless domain if the PHY and FPGA fundamentals are strong
Interview Process :
First round: Head of Product Development, R&D
Final round: Deepak (CEO)
If possible, a third round might happen
How to apply for this opportunity?
Step 1: Click On Apply! And Register or Login on our portal.
Step 2: Complete the Screening Form & Upload updated Resume
Step 3: Increase your chances to get shortlisted & meet the client for the Interview!
About Uplers:
Our goal is to make hiring reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant contractual onsite opportunities and progress in their career. We will support any grievances or challenges you may face during the engagement.
(Note: There are many more opportunities apart from this on the portal. Depending on the assessments you clear, you can apply for them as well).
So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!
Show more Show less