SP
Performance verifcation
Accepting applicationsSilicon Patterns · Bengaluru, Karnataka, India
Full-Time Mid_senior AIASICC++DDREthernet
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
India
Job Description: Performance Verification Engineer
Role Overview
We are seeking a Performance Verification Engineer to validate and optimize the performance of complex SoC/ASIC designs. The role focuses on analyzing system-level metrics like latency, throughput, bandwidth, and utilization, ensuring designs meet performance targets under real-world scenarios.
Key Responsibilities
Develop and execute performance verification plans for IP/SoC designs
Define and validate performance metrics (latency, bandwidth, throughput, QoS)
Build and run performance test scenarios (stress, corner cases, real workloads)
Analyze system-level behavior under different traffic and load conditions
Identify bottlenecks and work with design teams to optimize performance
Develop testbench infrastructure (SystemVerilog/UVM or C/C++ based) for performance analysis
Perform data collection, modeling, and visualization of performance metrics
Validate performance across different configurations and corner cases
Participate in performance tuning and architecture-level discussions
Automate regression and performance monitoring flows
Required Skills
Technical Skills
Strong understanding of computer architecture and SoC design
Experience in performance analysis conceptsLatency / Throughput
Bandwidth utilization
Buffering and congestion
QoS (Quality of Service)
Proficiency in:
SystemVerilog / UVM OR
C/C++ / Python (for modeling & analysis)
Experience with simulation/emulation tools
Strong debugging and data analysis skills
Understanding of memory systems, cache, interconnects (NoC)
Preferred Skills
Experience with high-speed interfaces (PCIe, DDR, Ethernet, AXI)
Familiarity with performance modeling tools or simulators
Experience in NoC (Network-on-Chip) performance validation
Knowledge of profiling tools and trace analysis
Exposure to AI/ML workload performance analysis (optional but valuable)
Educational Qualification
Bachelor’s or Master’s degree in Electronics / Electrical / Computer Engineering
Experience
5–10 years of experience in:
Performance verification / system validation / architecture modeling
Experience in SoC-level validation is highly desirable
Key Competencies
Strong problem-solving and analytical mindset
Ability to correlate system-level metrics with RTL behavior
Good collaboration skills with design, architecture, and software teams
Attention to detail in performance measurement and reporting
Nice-to-Have
Experience with emulation platforms (Palladium, Veloce, ZeBu)
Knowledge of hardware/software co-verification
Familiarity with Linux-based performance profiling tools
Data visualization skills (e.g., Python matplotlib, Excel dashboards)
Typical Day-to-Day Work
Creating performance test scenarios for traffic and workload modeling
Running simulations/emulations and collecting performance metrics
Debugging latency or throughput bottlenecks
Comparing measured vs expected performance targets
Presenting performance reports to stakeholders
Roles Where This JD Applies
SoC Performance Verification Engineer
System Validation Engineer
Architecture Performance Engineer
Pre-Silicon Performance Modeling Engineer
Show more Show less
Role Overview
We are seeking a Performance Verification Engineer to validate and optimize the performance of complex SoC/ASIC designs. The role focuses on analyzing system-level metrics like latency, throughput, bandwidth, and utilization, ensuring designs meet performance targets under real-world scenarios.
Key Responsibilities
Develop and execute performance verification plans for IP/SoC designs
Define and validate performance metrics (latency, bandwidth, throughput, QoS)
Build and run performance test scenarios (stress, corner cases, real workloads)
Analyze system-level behavior under different traffic and load conditions
Identify bottlenecks and work with design teams to optimize performance
Develop testbench infrastructure (SystemVerilog/UVM or C/C++ based) for performance analysis
Perform data collection, modeling, and visualization of performance metrics
Validate performance across different configurations and corner cases
Participate in performance tuning and architecture-level discussions
Automate regression and performance monitoring flows
Required Skills
Technical Skills
Strong understanding of computer architecture and SoC design
Experience in performance analysis conceptsLatency / Throughput
Bandwidth utilization
Buffering and congestion
QoS (Quality of Service)
Proficiency in:
SystemVerilog / UVM OR
C/C++ / Python (for modeling & analysis)
Experience with simulation/emulation tools
Strong debugging and data analysis skills
Understanding of memory systems, cache, interconnects (NoC)
Preferred Skills
Experience with high-speed interfaces (PCIe, DDR, Ethernet, AXI)
Familiarity with performance modeling tools or simulators
Experience in NoC (Network-on-Chip) performance validation
Knowledge of profiling tools and trace analysis
Exposure to AI/ML workload performance analysis (optional but valuable)
Educational Qualification
Bachelor’s or Master’s degree in Electronics / Electrical / Computer Engineering
Experience
5–10 years of experience in:
Performance verification / system validation / architecture modeling
Experience in SoC-level validation is highly desirable
Key Competencies
Strong problem-solving and analytical mindset
Ability to correlate system-level metrics with RTL behavior
Good collaboration skills with design, architecture, and software teams
Attention to detail in performance measurement and reporting
Nice-to-Have
Experience with emulation platforms (Palladium, Veloce, ZeBu)
Knowledge of hardware/software co-verification
Familiarity with Linux-based performance profiling tools
Data visualization skills (e.g., Python matplotlib, Excel dashboards)
Typical Day-to-Day Work
Creating performance test scenarios for traffic and workload modeling
Running simulations/emulations and collecting performance metrics
Debugging latency or throughput bottlenecks
Comparing measured vs expected performance targets
Presenting performance reports to stakeholders
Roles Where This JD Applies
SoC Performance Verification Engineer
System Validation Engineer
Architecture Performance Engineer
Pre-Silicon Performance Modeling Engineer
Show more Show less