GP
PD Solution Architect
Accepting applicationsGyanindit Pvt. Ltd. · Bengaluru, Karnataka, India
Full-Time Mid_senior AICadenceInnovusSoCSynopsys
Estimated market salary
₹22-40 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
India
Company Description Gyanindit Pvt. Ltd. is dedicated to the transformative power of knowledge and expertise, guided by the motto “Encouraging Empowerment.” The organization focuses on equipping individuals and organizations with the tools, guidance, and resources needed to succeed and grow. Through wide-ranging expertise, Gyanindit supports career advancement, organizational optimization, and technology-driven innovation. The team works to make a meaningful difference by delivering expert services that help clients achieve their goals and aspirations.
Hiring: PD Solution Architect
📍 Location: Bangalore
💼 Experience: 12+ Years
📌 Employment Type: Full-Time
This opportunity is with our client .
We are looking for an experienced PD Solution Architect to lead the physical design architecture and implementation strategy for complex SoCs. The ideal candidate will have deep expertise in advanced node physical design, implementation methodologies, and PPA optimization, along with experience in AI-driven EDA tools.
Key Responsibilities
Define physical implementation methodologies for large SoCs.
Develop SoC-level floorplanning and partitioning strategies.
Drive PPA (Performance, Power & Area) closure from specification to GDS-II.
Perform early feasibility, QoR, and implementation risk assessments.
Define clocking, power, and congestion strategies.
Guide global implementation teams and review signoff readiness.
Support customer technical discussions, solutioning, and project estimations.
Manage and deliver multiple physical design projects simultaneously.
Required Skills
12+ years of experience in Physical Design.
Hands-on experience with TSMC technology nodes (10nm and below).
Multiple successful SoC tape-outs on advanced nodes.
Strong expertise in floorplanning, CTS, timing closure, power optimization, and signoff methodologies.
Experience with Synopsys ICC2/Fusion Compiler and/or Cadence Innovus.
Experience with UPF and multi-voltage designs.
Hands-on experience with large SoCs (>100M gates).
Experience with HBM/HMC memory systems.
Experience with AI-based EDA tools such as Synopsys DSO.ai or Cerberus.
Preferred Skills
Experience with 5nm/3nm technology nodes.
Chiplet-based floorplanning.
3D-IC and advanced packaging.
HBM integration.
Automotive or HPC silicon experience.
If you meet the above requirements and are looking for an exciting opportunity to work on cutting-edge semiconductor designs, we would love to hear from you.
Show more Show less
Hiring: PD Solution Architect
📍 Location: Bangalore
💼 Experience: 12+ Years
📌 Employment Type: Full-Time
This opportunity is with our client .
We are looking for an experienced PD Solution Architect to lead the physical design architecture and implementation strategy for complex SoCs. The ideal candidate will have deep expertise in advanced node physical design, implementation methodologies, and PPA optimization, along with experience in AI-driven EDA tools.
Key Responsibilities
Define physical implementation methodologies for large SoCs.
Develop SoC-level floorplanning and partitioning strategies.
Drive PPA (Performance, Power & Area) closure from specification to GDS-II.
Perform early feasibility, QoR, and implementation risk assessments.
Define clocking, power, and congestion strategies.
Guide global implementation teams and review signoff readiness.
Support customer technical discussions, solutioning, and project estimations.
Manage and deliver multiple physical design projects simultaneously.
Required Skills
12+ years of experience in Physical Design.
Hands-on experience with TSMC technology nodes (10nm and below).
Multiple successful SoC tape-outs on advanced nodes.
Strong expertise in floorplanning, CTS, timing closure, power optimization, and signoff methodologies.
Experience with Synopsys ICC2/Fusion Compiler and/or Cadence Innovus.
Experience with UPF and multi-voltage designs.
Hands-on experience with large SoCs (>100M gates).
Experience with HBM/HMC memory systems.
Experience with AI-based EDA tools such as Synopsys DSO.ai or Cerberus.
Preferred Skills
Experience with 5nm/3nm technology nodes.
Chiplet-based floorplanning.
3D-IC and advanced packaging.
HBM integration.
Automotive or HPC silicon experience.
If you meet the above requirements and are looking for an exciting opportunity to work on cutting-edge semiconductor designs, we would love to hear from you.
Show more Show less