C
PD EMIR
Accepting applicationsCanvendor · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICSoCVLSI
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
India
#Urgent_Opening_for_Canvendor
#Hiring: PD EMIR (5+ Years Experience) | Chennai | Immediate to 15 Days
Job Title: PD EMIR
Years of Experience: 5+ Years
Location: Bengaluru/Hyderabad
Work Mode: WFO
Required Experience:
5+ years of overall VLSI/Physical Design experience is preferred.
3+ years of hands-on experience in PDN and EMIR closure for digital ASIC designs.
Strong expertise with industry-standard EMIR analysis and sign-off methodologies.
Excellent debugging, analytical, and cross-functional collaboration skills.
Key Responsibilities:
Own SoC-level IR Drop, Signal EM, and Power EM sign-off for complex digital ASIC designs.
Drive EMIR closure by identifying root causes of power integrity and electromigration violations.
Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign-off.
Collaborate closely with the Physical Design (PD) team to drive efficient IR/EM closure across the chip.
Analyze power delivery networks (PDN) and recommend improvements for robust power integrity.
Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets.
If interested kindly share your updated CV to [email protected]
Show more Show less
#Hiring: PD EMIR (5+ Years Experience) | Chennai | Immediate to 15 Days
Job Title: PD EMIR
Years of Experience: 5+ Years
Location: Bengaluru/Hyderabad
Work Mode: WFO
Required Experience:
5+ years of overall VLSI/Physical Design experience is preferred.
3+ years of hands-on experience in PDN and EMIR closure for digital ASIC designs.
Strong expertise with industry-standard EMIR analysis and sign-off methodologies.
Excellent debugging, analytical, and cross-functional collaboration skills.
Key Responsibilities:
Own SoC-level IR Drop, Signal EM, and Power EM sign-off for complex digital ASIC designs.
Drive EMIR closure by identifying root causes of power integrity and electromigration violations.
Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign-off.
Collaborate closely with the Physical Design (PD) team to drive efficient IR/EM closure across the chip.
Analyze power delivery networks (PDN) and recommend improvements for robust power integrity.
Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets.
If interested kindly share your updated CV to [email protected]
Show more Show less