LT
PCIE Verification Engineer
Accepting applicationsLeadSoc Technologies Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Mid_senior CadenceMentorPCIEPCIePerl
Posted
6d ago
Category
Verification
Experience
Mid_senior
Country
India
Verification Engineer – PCI Express (PCIe Gen5/Gen6/Gen7)
Experience 5–15+ Years
Location- Bangalore
Job Summary
We are looking for an experienced Verification Engineer with strong expertise in PCI Express (PCIe) Gen5, Gen6, and exposure to Gen7 specifications. The candidate will lead the verification of high-speed PCIe IPs and SoCs, drive verification strategy, develop reusable UVM-based environments, and ensure first-pass silicon success through comprehensive verification methodologies.
Key Responsibilities
Lead end-to-end functional verification of PCIe Controller, PHY, and Subsystem IPs supporting PCIe Gen5/Gen6 and next-generation Gen7.
Define verification architecture, methodology, verification plans, and project execution strategy.
Develop reusable verification environments using SystemVerilog and UVM.
Create constrained-random testcases, assertions, scoreboards, protocol checkers, and functional coverage models.
Verify PCIe protocol layers including Transaction Layer, Data Link Layer, and Physical Layer.
Validate LTSSM, link training, equalization, flow control, replay mechanisms, error handling, configuration space, MSI/MSI-X, power management, and reset scenarios.
Verify advanced PCIe capabilities such as SR-IOV, ATS, PASID, PRI, ARI, IDE, DOE, FLIT Mode, PAM4 awareness, L0p, and multi-lane configurations (x1/x2/x4/x8/x16).
Perform regression planning, debugging, coverage analysis, and verification closure.
Collaborate with architecture, RTL, firmware, validation, and physical design teams to resolve functional issues.
Drive verification reviews, code quality, and sign-off activities.
Mentor junior engineers and provide technical leadership throughout the project lifecycle.
Technical Skills
Strong expertise in SystemVerilog and UVM.
Experience with constrained-random verification, assertions (SVA), functional coverage, and coverage-driven verification.
Excellent understanding of PCIe architecture and protocols across Gen4, Gen5, and Gen6, with exposure to Gen7.
In-depth knowledge of LTSSM, TLP/DLLP, Ordered Sets, Flow Control, Credits, Replay Buffer, Equalization, Link Training, FEC, FLIT Mode, IDE, and Power Management.
Experience using industry-standard PCIe Verification IPs (Synopsys, Cadence, Siemens, Avery, or equivalent).
Hands-on experience with simulators such as VCS, Xcelium, or Questa.
Strong debugging skills using Verdi, DVE, or SimVision.
Proficiency in Python, Perl, Shell, or Tcl scripting.
Familiarity with version control systems such as Git or Perforce and CI tools like Jenkins.
Notice Period- immediate to 30 days
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Experience 5–15+ Years
Location- Bangalore
Job Summary
We are looking for an experienced Verification Engineer with strong expertise in PCI Express (PCIe) Gen5, Gen6, and exposure to Gen7 specifications. The candidate will lead the verification of high-speed PCIe IPs and SoCs, drive verification strategy, develop reusable UVM-based environments, and ensure first-pass silicon success through comprehensive verification methodologies.
Key Responsibilities
Lead end-to-end functional verification of PCIe Controller, PHY, and Subsystem IPs supporting PCIe Gen5/Gen6 and next-generation Gen7.
Define verification architecture, methodology, verification plans, and project execution strategy.
Develop reusable verification environments using SystemVerilog and UVM.
Create constrained-random testcases, assertions, scoreboards, protocol checkers, and functional coverage models.
Verify PCIe protocol layers including Transaction Layer, Data Link Layer, and Physical Layer.
Validate LTSSM, link training, equalization, flow control, replay mechanisms, error handling, configuration space, MSI/MSI-X, power management, and reset scenarios.
Verify advanced PCIe capabilities such as SR-IOV, ATS, PASID, PRI, ARI, IDE, DOE, FLIT Mode, PAM4 awareness, L0p, and multi-lane configurations (x1/x2/x4/x8/x16).
Perform regression planning, debugging, coverage analysis, and verification closure.
Collaborate with architecture, RTL, firmware, validation, and physical design teams to resolve functional issues.
Drive verification reviews, code quality, and sign-off activities.
Mentor junior engineers and provide technical leadership throughout the project lifecycle.
Technical Skills
Strong expertise in SystemVerilog and UVM.
Experience with constrained-random verification, assertions (SVA), functional coverage, and coverage-driven verification.
Excellent understanding of PCIe architecture and protocols across Gen4, Gen5, and Gen6, with exposure to Gen7.
In-depth knowledge of LTSSM, TLP/DLLP, Ordered Sets, Flow Control, Credits, Replay Buffer, Equalization, Link Training, FEC, FLIT Mode, IDE, and Power Management.
Experience using industry-standard PCIe Verification IPs (Synopsys, Cadence, Siemens, Avery, or equivalent).
Hands-on experience with simulators such as VCS, Xcelium, or Questa.
Strong debugging skills using Verdi, DVE, or SimVision.
Proficiency in Python, Perl, Shell, or Tcl scripting.
Familiarity with version control systems such as Git or Perforce and CI tools like Jenkins.
Notice Period- immediate to 30 days
Show more Show less