PCIe Engineer

HCLTech is looking for a highly talented and self- motivated PCIe Engineer to join it in advancing the technological world through innovation and creativity.

Job Title: PCIe Engineer
Job REQ ID: 134203
Position Type: Full Time
Location : Sunnyvale CA (Onsite)

Job Description:

Key Responsibilities
Pre-Silicon
Develop and execute test plans for PCIe Gen3/Gen4/Gen5/Gen6 IP blocks and SoC-level integration
Create directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality
Perform protocol-level analysis using VIP (Verification IP) environments and bus functional models
Debug RTL-level issues related to link training, power management (ASPM, L-states), equalization, and error handling
Collaborate with design teams on coverage closure, assertions, and functional coverage models

Post-Silicon
Bring up and validate PCIe links on silicon platforms (FPGA, emulation, and first silicon)
Develop and execute post-silicon validation test plans covering link training, enumeration, data integrity, error injection, and compliance
Debug silicon-level issues using protocol analyzers (e.g., Keysight, Teledyne LeCroy), oscilloscopes, and logic analyzers
Perform root-cause analysis of PCIe link failures, packet errors, and performance degradation
Characterize PCIe PHY performance including jitter, eye diagrams, and signal integrity
Collaborate with platform, firmware, and BIOS teams to resolve system-level PCIe issues
Drive compliance and interoperability testing per PCI-SIG specifications

General
Analyze PCIe specification updates and assess impact on existing IP/SOC designs
Automate test infrastructure, result parsing, and regression frameworks
Document findings, debug methodologies, and test coverage metrics
Contribute to team knowledge sharing

Required Qualifications
Education: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field
Experience: 3–8+ years of experience in PCIe validation, verification, or silicon bring-up
Strong understanding of PCIe specification (Gen3 through Gen5/Gen6), including:
Transaction Layer: TLP types, ordering rules, flow control, completion handling
Data Link Layer: ACK/NAK, replay, LCRC, DLLP
Physical Layer: Link training (LTSSM), equalization, encoding (8b/10b, 128b/130b)
Power management: ASPM, L-states, D-states
Proficiency in System Verilog/UVM for pre-silicon test development
Experience with protocol analyzers and lab debug tools for post-silicon validation
Familiarity with scripting languages (Python, Perl, Tcl) for test automation and log parsing
Solid understanding of PCIe enumeration, BAR programming, and configuration space
Experience with FPGA prototyping or emulation platforms is a plus
Preferred Qualifications
Experience with CXL (Compute Express Link) or other PCIe-based protocols
Knowledge of signal integrity concepts (S-parameters, eye diagrams, jitter analysis)
Familiarity with compliance testing per PCI-SIG specifications and test suites
Experience with NVMe, CCIX, or UCIe protocols
Background in SoC-level integration and system-level validation
Understanding of BIOS/firmware interactions with PCIe subsystems
Contributions to PCIe IP development or architecture definition


Pay and Benefits
Pay Range Minimum: $78000/annum
Pay Range Maximum: $148000/annum

HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to secure@hcltech.com for investigation.

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year

How You’ll Grow
At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best
you best

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