Package Design Engineer

**Relocation Assistance provided for the right candidate**

Elite Connector is excited to partner with a worldwide leader in the Semiconductor industry to find a Package Design Engineer near Orlando, FL.

Essential Duties and Responsibilities:

• The primarily responsible for design of advanced semiconductor packages, including both ceramic and organic substrates, including layout, parasitic extraction, and optimization
• Layout of a Semiconductor Package that involves flip chip dies, wire bond dies, resistors, capacitors, on a substrate (primarily ceramic, sometimes organic) – Using tool like Cadence Allegro Advanced Package Designer Plus (APD+) - Ability to take Schematic & NET List as input and start the Layout - Ability to do Schematic Capture based on PDF or sketch is added bonus (This is 75% of this role)
• Package Lid Design – done in Solidworks
• Electrical Simulations (done in add-on Modules like Cadence Celsius PowerDC, Sigrity PowerDC)
• Mechanical analysis – structural & Thermal – usually done in Ansys tool
• Work with IC design, system design, package Signal Integrity (SI)/Power Integrity (PI) & thermal engineering teams to design custom interposer and substrates
• Work with SoC design teams to optimize die floorplan, bump patterns and interposer / substrate stack up
• Work with IC design team to define IC package requirements
• Design package layout using standard CAD tools
• Extract package parasitics and conduct PI/SI analysis

Preferred Knowledge, Skills, And Abilities

Layout:

• Allegro Package Designer Plus (APD+) tools for designing the package and generating artwork for fabrication.

Analysis:

• Celsius PowerDC (IR Drop)
• Sigrity Advanced SI II: Analysis tools for Signal integrity of parallel busses ( DDRx) and serial links (PCIe Gen x), including Package and PCB effects
• Sigrity Advanced PI II: Power Integrity tools ( IR drop, Impedance Profile, capacitor optimization) including Package and PCB effects

RF / Microwave Design

• AWR, Momentum and HFSS Software Circuit, system, and EM simulation for RF/microwave product development

Qualifications

• Bachelors degree in Electrical Engineering, Mechanical Engineering, or other semiconductor packaging related discipline.
• 5+ years of experience in semiconductor packaging design, modeling, and simulations
• Strong authority on Cadence Allegro Package Designer Plus (APD+)
• Experience on interposer and substrate layouts and design in advanced package technologies
• Experience with 2.5D, 3D package design
• Experience with design teams on floor plan, bump and layout optimization
• Good experience with SI/PI tools for package level extraction/simulation