NoC Design Verification Engineer

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

Responsibilities

Develop and execute verification plans for NoC and coherent interconnect IP/subsystems
Build UVM/SystemVerilog-based verification environments, testbenches, checkers, scoreboards, assertions, and functional coverage
Verify multiple NoC configurations, topologies, routing scenarios, and protocol interactions
Create assertions, checkers, and coverage aligned with evolving NoCLink specifications and configuration requirements
Drive verification for subsystem integration involving memory fabrics, cache/coherency paths, and large SoC interconnects
Partner with design and architecture teams to review specifications and convert them into actionable test plans
Debug simulation failures, isolate root cause, and work with RTL/design teams on closure
Track verification progress using metrics such as coverage, bug trends, and testplan completion
Contribute to development of VIP/interfaces and reusable DV components for interconnect verification
Support regression bring-up, test triage, and verification closure activities

Required Qualifications

4+ years of experience with a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
Strong experience in Design Verification using SystemVerilog and UVM
Experience verifying interconnects, NoCs, memory subsystems, cache/coherency logic, or large SoC subsystems
Good understanding of verification methodologies including test planning, constrained-random verification, assertions, coverage, and regression debug
Experience writing SVA/assertion-based checks and functional coverage models
Strong debugging skills across RTL, testbench, and simulation environments
Solid understanding of computer architecture and on-chip data movement

Preferred Qualifications

Experience with coherent interconnects, NoC fabrics, or memory fabrics
Familiarity with protocol/interface verification and VIP development
Experience with subsystem- or SoC-level verification in multicore or high-performance designs
Exposure to performance, stress, corner-case, and configuration-based verification
Familiarity with scripting using Python, Perl, or shell
Experience collaborating across global design and DV teams

What You’ll Work On

Verification of NoCLink-related functionality across different configurations
Development of assertions/checkers/coverage for updated NoC specifications
Support for VIP/interface definition work, signal dependency understanding, and configuration-driven verification
Verification strategy and execution for scalable on-chip communication fabrics

Nice to Have

Experience with formal verification, CDC-related verification planning, or protocol compliance checking
Understanding of cache coherency and high-bandwidth data paths
Prior experience in CPU, subsystem, or SoC verification environments

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
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