C
Multiple Post Silicon Validation Engineer roles (grades T4 to T6)
Accepting applicationsCadence · Bengaluru, Karnataka, India
Full-Time Entry AnalogC++CadenceDDRFPGA
Posted
4d ago
Category
Test
Experience
Entry
Country
India
There are multiple openings for Post Silicon Validation Engineer roles (grades T4 to T6, ie, Principal Test Engineer to Test Architect) in High Speed SERDES Physical Layer Electrical Validation Domain at Cadence Design Systems, Bangalore. The roles are intended for candidates with direct experience in this domain in the range 6 years to 18 years (depending upon the job grade targeted)
Why choose Cadence Design Systems? These roles offer the opportunity to work on the post silicon electrical validation of various cutting edge high speed SERDES and Die to Die designs. Apart from the challenging work and opportunity for gain deep knowledge in these technologies, Cadence also offers attractive compensation packages.
What we are looking for in potential candidates is listed below.
Minimum Qualifications:
• BTECH/MTECH in in an Electronics stream with experience between 6-18 years (depending upon the job grade targeted) in Post-Silicon Physical Layer Electrical Validation
• Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc
• Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc
Preferred Qualifications:
• Experience managing small teams (at least 2 members and above) is a strong plus for T4 grade and above roles
• Experience leading the complete post silicon validation efforts for at least one full project is a strong plus for T4 grade and above roles
• 1-2 years of experience in Analog, PLL,FPGA Design, PCB schematic and layout design & Prototyping is a strong plus
• Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.
• Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL
• Experience conducting hiring interviews and mentoring new hires
• Candidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects.
Show more Show less
Why choose Cadence Design Systems? These roles offer the opportunity to work on the post silicon electrical validation of various cutting edge high speed SERDES and Die to Die designs. Apart from the challenging work and opportunity for gain deep knowledge in these technologies, Cadence also offers attractive compensation packages.
What we are looking for in potential candidates is listed below.
Minimum Qualifications:
• BTECH/MTECH in in an Electronics stream with experience between 6-18 years (depending upon the job grade targeted) in Post-Silicon Physical Layer Electrical Validation
• Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc
• Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc
Preferred Qualifications:
• Experience managing small teams (at least 2 members and above) is a strong plus for T4 grade and above roles
• Experience leading the complete post silicon validation efforts for at least one full project is a strong plus for T4 grade and above roles
• 1-2 years of experience in Analog, PLL,FPGA Design, PCB schematic and layout design & Prototyping is a strong plus
• Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.
• Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL
• Experience conducting hiring interviews and mentoring new hires
• Candidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects.
Show more Show less