Memory System Designer and Place and Route Engineer

Job Description:

We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 8 years of relevant experience and a Bachelor in Electrical Engineering.

Job Responsibilities


Architect and design memory subsystems
Implement RTL of subsystem designs
Place and route (physical design)
Design closure: timing, DRC, LVS, EM/IR, etc.
Gate netlist synthesis


Skill Set Required


Strong design skills
Ability to write and debug Verilog RTL code
Place and route expertise
Proficient in running STA, DRC, EM/IR tools, and attaining design closure
Ability to code in Python
Good understanding of synthesis tools and running synthesis
Capable of running and debugging logical equivalency checkers
Familiar with memory behavior
Proficient in writing automation scripts, and tools savvy
Good communication, interpersonal, and leadership skills
Motivated, self-driven, and good at multitasking


Additional Job Description:

Compensation And Benefits

The annual base salary range for this position is $108,000 - $172,800

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

R026060

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