Memory Layout Engineers

Memory Layout Engineer – TSMC Advanced Nodes

Location: Bangalore
Experience: 3–7 Years
Notice Period: Immediate / 30 Days Joiners Preferred
Employment Type: Full-Time [5days WFO]

Mandatory Skills

3–7 years of experience in Memory Layout (SRAM / DRAM / Bitcell Layout)
Strong hands-on experience in TSMC 2nm / 3nm / 5nm technology nodes
Expertise in SRAM and DRAM memory layout design and implementation
Strong knowledge of Virtuoso / Layout environment
Good understanding of DRC, LVS, PEX, ERC, DFM
Strong understanding of advanced CMOS layout rules, matching, symmetry, density, and parasitic effects
Strong debugging and problem-solving skills in memory layout issues

Share your updated resume to vagdevi@semi-leaf.com
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