SI
Memory Layout Design Engineer
Accepting applicationsSysTechCorp Inc · Hyderabad, Telangana, India
Full-Time Entry Memory DesignLayoutFinFETPhysical VerificationDRC
Estimated market salary
₹9-16 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
10h ago
Category
Verification
Experience
Entry
Country
India
Title: Memory Layout Design Engineer.
Experience: 3+ years.
Location: Bangalore(F2F).
Roles and Responsibilities:
Memory Leaf cell layout library design from scratch including top level integration.
Good knowledge on different types of memory architectures.
Good knowledge in optimized layout design for better performance.
Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.
Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.
Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.
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Experience: 3+ years.
Location: Bangalore(F2F).
Roles and Responsibilities:
Memory Leaf cell layout library design from scratch including top level integration.
Good knowledge on different types of memory architectures.
Good knowledge in optimized layout design for better performance.
Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.
Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.
Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.
Show more Show less