Member of Technical Staff - Performance Modeling

Infinity Artificial Intelligence Institute San Francisco Bay Area

Member of Technical Staff - Performance Modeling

Infinity Artificial Intelligence Institute San Francisco Bay Area

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Member of Technical Staff - Performance Modeling

Company: Infinity

Team: Systems / AI Infrastructure
Location: San Francisco (on-site)
Type: Full-time

The Mission

Everything upstream of us is gated by one scarce resource: the chip itself. A part is under NDA, or taped out but not yet back from the fab, or there are four boards on earth and all four are booked. That scarcity sets the pace of the entire company, until you take the hardware off the critical path.

That is what the simulator does. It runs on ordinary CPUs and reproduces an AI accelerator’s behavior faithfully enough that Ignition, our bringup agent, can write a compiler backend, and a matmul kernel against it, and Infy, our inference library, can prove a kernel correct, all before the silicon is in the building. Because it runs on CPUs, it scales on infrastructure we already own: hundreds of simulated chips are cheaper, and far more available, than a single reserved board.

This is the substrate the rest of the stack stands on. Every gate in our test ladder runs on real hardware and in simulation at the same time, so a kernel that passes on a chip we have can be trusted on one we don’t yet. The simulator is what lets a brand-new architecture join it months before its first board ships. The same machine has already done the hard version in production.

What you’ll work on

You’ll Own The Models The Rest Of The Stack Builds And Validates Against. Which Of These You Take Depends On Your Strengths

Data-placement and movement tracking. Model exactly what sits in which memory at each step and every transfer between units. This is what elevates the simulator from “runs the ops” to “catches the bugs”: ordering hazards and race conditions that only appear on real silicon under precisely the wrong schedule become reproducible and inspectable here.
Performance and timing models. Capture enough of the memory hierarchy, execution units, and interconnect to predict throughput and quantify the gap to peak with no physical part in hand. Because the model observes every stall and every byte moved, its benchmarks rest on mechanism rather than curve-fitting, and moving them from plausible to trustworthy is where much of the difficulty lives.
Coverage across execution models. Warp-based GPUs, scalar tile meshes, dataflow arrays, flat SIMD, analog MAC, wafer-scale: each demands a different simulator skeleton. The leverage is in the shared abstractions, an execution-model-neutral core a new architecture can slot into instead of forcing a rewrite.
Continuous fidelity checking. Design the reconciliation loop that pins each model to its silicon: bootstrap from a spec or fuzzer output, then, whenever a board is available, diff the simulator against the real chip and drive any divergence to zero before it spreads.
Functional and ISA-level modeling. Take a spec, or more often the behavioral model our probes and ISA fuzzer assemble from a chip with no complete spec, and turn it into an executable that runs the instruction set with correct semantics and can be checked bit-for-bit against a reference. This is the layer everything else trusts.
RTL co-simulation. Stand up Verilator or Icarus Verilog against a vendor’s RTL or a partial model and wire it into the same test harness the physical part uses, so a design can be validated before first silicon exists.
The golden reference. The simulator is the oracle the entire test ladder trusts, which makes its correctness non-negotiable: a wrong reference doesn’t merely fail, it silently certifies broken code as correct. Owning this means owning that standard.
Speed and scale. A model no one can afford to run is a model no one uses. JIT compilation, parallel execution, per-layer fidelity that spends cycles only where they matter, and horizontal scale-out across CPU fleets so that hundreds of simulated chips cost less than one reserved board.
Integration with the agent loop. Expose the same hardware schema, probes, and interfaces the agent sees on real targets, so Ignition cannot tell whether it is driving silicon or a simulation until the moment that distinction actually matters.

What we’re looking for

We weight range and depth over any particular résumé. Strong candidates will have most of the following:

Working computer-architecture intuition. Not a textbook recall of pipelines and memory hierarchies, but a felt sense of what actually determines throughput and where the stalls hide.
You’ve built or extended a simulator or emulator, functional or cycle-accurate: gem5, QEMU, Spike, Verilator, or something you wrote from scratch.
You’re comfortable when the spec is incomplete or wrong. Reverse-engineering real behavior, reconciling a datasheet that disagrees with the silicon, and shipping a model you can defend anyway is the normal case here, not the exception.
Fluency in Python and a systems language: C, C++, or Rust.
A test-first instinct. You understand, without being told, that the thing everything else is measured against has to be held to a higher standard than the code it measures.

Nice to have

Built an ISA simulator or emulator end to end.
A hardware-design background: HLS, Verilog, or time on the vendor side of a chip.
Familiarity with non-GPU execution models; the more exotic, the better.
Performance modeling or roofline analysis as part of your regular practice.
Experience building with coding agents, and calibrated judgment about where the model is trustworthy and where the tests have to catch it.

Who we are

Infinity is an early-stage AI infrastructure research company building the software layer that makes non-NVIDIA chips competitive for AI inference. Rather than relying on scarce human kernel engineers, we use AI to automatically generate, test, and optimize the low-level code that determines how efficiently a chip runs AI models. We’ve signed or are negotiating design partnerships with d-Matrix, AMD, AWS Trainium, Microsoft (Maia and Nexus), Qualcomm, and others. Founded by Jeremy Nixon (former Google Brain; co-founder of AGI House with Andrej Karpathy), Infinity has raised $15M from investors including the founder of Intercom, the VP of AI at AMD, and the founder of MLCommons. We’re headquartered in San Francisco.

Seniority level Mid-Senior level
Employment type Full-time
Job function Engineering and Information Technology
Industries Software Development

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