Member of Technical Staff, Hardware

ITAR Notice: This role involves access to ITAR-controlled information. Applicants must be U.S. persons (U.S. citizens, U.S. permanent residents, asylees, or refugees) per 22 CFR 120.62.

What Will You Do

Land somewhere across the DensityAI hardware org — RTL design, design verificaCon (SOC, AI Core, formal, or general DV), physical design, DFT / manufacturing test, performance modeling and verificaCon, advanced packaging, or post-silicon bring-up.

The specialized roles are posted separately; this one is for engineers who span more than one of them, or who don't fit one lane cleanly. We'll do the sub-team match during interviews.

Use and develop AI assisted tool flows to accelerate whichever discipline you land in.

What We're Looking For

You bring exceptional SystemVerilog and Verilog skills at production grade, and you're comfortable reading complex testbenches and the RTL they exercise
You have 5+ years of production silicon experience, including at least one production tape-out that you contributed to meaningfully — with responsibility that extended into post-silicon debug
You understand the end-to-end ASIC flow, from RTL through synthesis, place & route, and signoff
You have strong computer-architecture fluency across pipelines, caches, memory hierarchies, and NoC topologies
You're comfortable with ambiguity — the specific sub-team match happens during the interview process
(Optional) It's a plus if you bring experience with UVM and constrained-random verification, formal methods (SVA, JasperGold, VC Formal), industry-standard EDA tools (VCS, Verdi, Innovus, Fusion Compiler, PrimeTime, Tempus, Tessent), advanced process nodes (7nm or better), DFT methodology, multi-die packaging (CoWoS, EMIB, 2.5D/3D, HBM), signal/power integrity, RISC-V, performance modeling, or scripting (Python, Tcl)

Full compensation packages are based on candidate experience and relevant certifications.

California pay range

$70,000 - $70,000 USD
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