A
Member of Technical Staff - Data & Evals
Accepting applicationsArchitect · Palo Alto, CA
Full-Time Senior AIASICSystemVerilogaiate
Posted
1d ago
Category
Design
Experience
Senior
Country
United States
About Architect
Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new era of domain-specific chips that unlock capabilities impossible with current hardware paradigms. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel.
What You'll Do
As a Member of the Technical Staff - Data at Architect, you will own the architecture and execution of our data pipelines and evaluation suites. You will build the foundation that ensures our models generate high-quality, verified chip designs.
Architect and build synthetic data pipelines for both RL & SFT model training.
Collaborate closely with research teams to understand evolving data needs and iterate quickly on collection methods.
Build and maintain comprehensive evaluation suites that ensure model quality and consistency.
Partner closely with hardware engineers, research engineers, and agent software engineers to ensure new datasets meet quality and diversity standards.
Think deeply about the experience of the annotators/experts , build clear and efficient interfaces that will lead to high-quality hardware data.
Prioritize and juggle multiple work streams, making trade-off decisions in a fast-moving environment where research priorities can shift quickly.
What We'd Like To See
Qualifications & Skills:
Expertise with hardware design: Must have fundamental understanding of computer architecture, chip design, HDL like SystemVerilog, with relevant degrees in MS/PhD or industry-level exposure/experience.
Data Pipelines & Infrastructure: Experience building human data labeling interfaces, or scalable data collection pipelines. Solid engineering skills with broad experience across the stack.
AI/ML Familiarity: Familiarity with how preference data, RLVR/RLHF, and reward models are used in AI model training.
Tooling & User Experience: Proven track record of building and improving the user-experience of internal tools, particularly those involving interactive annotation workflows.
Collaboration: Experience working effectively with researchers who are internal users/customers. You thrive in fast-moving environments and balance speed of iteration with long-term system health.
Bonus
Publications or open-source contributions in ML evaluation frameworks.
Publications or open-source contributions in hardware design (HDL, high-level synthesis, or physical-design) or chip design methodologies.
Background working at leading EDA/chip-design companies, or AI chip startups.
What We Offer
Competitive salary and meaningful equity stake
Fast-paced startup with autonomy and visible impact
Cutting-edge AI-driven chip design challenges
Show more Show less
Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new era of domain-specific chips that unlock capabilities impossible with current hardware paradigms. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel.
What You'll Do
As a Member of the Technical Staff - Data at Architect, you will own the architecture and execution of our data pipelines and evaluation suites. You will build the foundation that ensures our models generate high-quality, verified chip designs.
Architect and build synthetic data pipelines for both RL & SFT model training.
Collaborate closely with research teams to understand evolving data needs and iterate quickly on collection methods.
Build and maintain comprehensive evaluation suites that ensure model quality and consistency.
Partner closely with hardware engineers, research engineers, and agent software engineers to ensure new datasets meet quality and diversity standards.
Think deeply about the experience of the annotators/experts , build clear and efficient interfaces that will lead to high-quality hardware data.
Prioritize and juggle multiple work streams, making trade-off decisions in a fast-moving environment where research priorities can shift quickly.
What We'd Like To See
Qualifications & Skills:
Expertise with hardware design: Must have fundamental understanding of computer architecture, chip design, HDL like SystemVerilog, with relevant degrees in MS/PhD or industry-level exposure/experience.
Data Pipelines & Infrastructure: Experience building human data labeling interfaces, or scalable data collection pipelines. Solid engineering skills with broad experience across the stack.
AI/ML Familiarity: Familiarity with how preference data, RLVR/RLHF, and reward models are used in AI model training.
Tooling & User Experience: Proven track record of building and improving the user-experience of internal tools, particularly those involving interactive annotation workflows.
Collaboration: Experience working effectively with researchers who are internal users/customers. You thrive in fast-moving environments and balance speed of iteration with long-term system health.
Bonus
Publications or open-source contributions in ML evaluation frameworks.
Publications or open-source contributions in hardware design (HDL, high-level synthesis, or physical-design) or chip design methodologies.
Background working at leading EDA/chip-design companies, or AI chip startups.
What We Offer
Competitive salary and meaningful equity stake
Fast-paced startup with autonomy and visible impact
Cutting-edge AI-driven chip design challenges
Show more Show less