Manager - Design Engineering

🔹 Key Responsibilities

Design and develop synthesizable RTL using Verilog/System Verilog
Translate architecture specifications into micro-architecture and RTL implementation
Develop high-performance and low-power digital design blocks
Work closely with verification teams for functional validation and debug
Perform design reviews and ensure coding quality and design guidelines
Collaborate with physical design teams to meet timing, power, and area requirements
Debug RTL issues and support silicon bring-up when required

🔹 Required Skills

Strong expertise in Verilog and System Verilog
Solid understanding of digital design fundamentals and computer architecture
Experience with AMBA protocols such as AXI, AHB, and APB
Knowledge of synthesis, timing closure, and low-power design techniques
Familiarity with simulation and debugging tools
Experience working in ASIC/SoC design environments

🔹 Preferred Qualifications

Strong debugging and problem-solving skills
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Strong understanding of digital logic design principles.
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