Low power design(NPU) lead

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

Hands on experience in writing UPF based on power spec for block/SOC having complex power crossings
Hands on experience in validating power intent using CLP
Hands on experience on Power analysis using PTPX
Understanding on issues related to MV cell (isolation, level shifter, retention etc) insertion during synthesis
Good understanding on optimization of dynamic & leakage power during RTL development and physical implementation
Good understanding on power correlation between Pre-Si and Post-Si
Automation skill in TCL and/or Perl
Good communication skill


Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.


OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Creating power spec for Qualcomm DSP IPs based on the design spec
Power intent development using UPF for DSP IPs based on power spec
Power intent validation at RTL level , Gate level (synthesis , PD ) using CLP
Fixing power intent based on PA DV feedback for any issue related to power intent Debugging issues related to MV cell insertion during synthesis and modifying UPF accordingly
Dynamic and Leakage power projection of DSP IPs during starting of the project
Dynamic and Leakage power no. generation using PTPX and tracking the same at different stages of implementation flow
Highlighting issues related to dynamic and leakage power mismatch compared to the target and working with Synthesis and PD teams to fix the issues
Working with cross function teams (SOC, Sub System etc) for smooth handoff of power intent and Dynamic & leakage power no. at different stages of project execution


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