Low Power Design Engineer ( 6+ Years )

Title :: UPF & VCLP Low Power Design Engineer
Location :: San Jose, CA


JOB DESCRIPTION
This role requires a strong background in low power design implementation, with specific emphasis on using/developing UPF to drive power-aware signoff

.
Power Specification and UPF Development: Work with architects and logic designers to understand power requirements, define power specifications, and develop the Unified Power Format (UPF
).Low Power Implementatio
n:Use Design Compiler (DC) to perform low-power insertion, debug & identify issues with low power cells insertion, and update the U
PFImplement low power insertion techniques, including the automatic insertion of retention flops, isolation cells, and level shifters during synthesis (DC-VCLP flow), formal verification tool
s.Support UPF for design, DV, Synthesis, Formality, DFT and PNR team
s.Verification and Sign-off (VCLP/Formal
):Verify and sign-off the low power intent using low power checking tools such as VCLP or C
LPDebug and resolve UPF validation and low power rule violations, including issues related to retention, level shifters and isolation rul
esDebug and understand formal verification issues related to the low power inten
t.Required Skills and Experien
ceHands-on experience in defining power intent using U
PFProficiency in low power verification using VCLP/CL
P.Expertise in synthesis with low power cell insertion (e.g., isolation, level shifters, retention) using tools like Desi

gn
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