ST
Lead Static Timing Analysis (STA) Engineer
Accepting applicationsSykatiya Technologies Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICCadenceDFTJTAGPython
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
Role Overview
We are seeking a highly skilled Lead Static Timing Analysis (STA) Engineer to drive timing closure and signoff for our next-generation, high-performance ASIC/SoC designs. In this role, you will be technical lead for multi-corner, multi-mode (MCMM) timing signoff across ultra-low power and high-speed clock domains. You will collaborate closely with RTL Design, Physical Design, Synthesis, DFT, and CAD methodology teams to define timing constraints, debug complex timing paths, and ensure zero-delay signoff readiness on advanced process nodes.
Key Responsibilities
Technical Leadership & Timing Signoff
• Constraints Management: Define, write, and validate complete SDC (Synopsys Design Constraints) for multi-mode, multi-corner (MCMM) timing views, including complex clock domain crossings (CDC) and false/multicycle paths.
• Full-Chip & Block STA: Lead block-level and full-chip timing closure, performing Static Timing Analysis across all process, voltage, and temperature (PVT) corners.
• Signal Integrity & Noise Analysis: Drive crosstalk analysis, glitched clock/data detection, noise analysis, and On-Chip Variation (OCV/AOCV/POCV) modeling.
• EOC & ECO Generation: Generate, validate, and integrate timing Engineering Change Orders (ECOs) using automated functional/leakage ECO techniques to achieve post-route timing closure without sacrificing area or power budget.
• Methodology & Flow Setup: Architect and optimize signoff STA methodology, script automation (Tcl/Python), and CAD flow integration for high-efficiency runtimes.
Cross-Functional Collaboration
• Work with the RTL & Architecture teams to resolve structural timing bottlenecks and critical path constraints early in the design cycle.
• Partner with Physical Design engineers to guide floorplanning, clock tree synthesis (CTS) strategies, and routing optimizations.
• Coordinate with DFT Engineers to set up and close timing for Scan, MBIST, and JTAG modes.
• Interface with EDA vendors to evaluate advanced STA tools and resolve tool/flow anomalies.
Required Qualifications
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, VLSI Design, or a related technical field.
• Experience: 8+ years of dedicated hands-on experience in Static Timing Analysis (STA) with a track record of multiple successful tape-outs on advanced nodes (7nm, 5nm, 3nm).
• Core STA Expertise:
o In-depth knowledge of MCMM timing analysis, AOCV/POCV, derating methodologies, signal integrity (crosstalk delta-delay and noise), and IR-drop impact on timing.
o Comprehensive understanding of complex clock topologies, clock domain crossings, and asynchronous interfaces.
o Proficient in manual and automated ECO flows (Hold/Setup fixes, leakage recovery).
• Tool Mastery:
o Synopsys: PrimeTime, PrimeTime-SI, PrimeTime-PX.
o Cadence: Tempus Timing Signoff Solution.
• Scripting: Advanced proficiency in Tcl and Python for flow development, reporting, and automated timing fix generation.
Show more Show less
We are seeking a highly skilled Lead Static Timing Analysis (STA) Engineer to drive timing closure and signoff for our next-generation, high-performance ASIC/SoC designs. In this role, you will be technical lead for multi-corner, multi-mode (MCMM) timing signoff across ultra-low power and high-speed clock domains. You will collaborate closely with RTL Design, Physical Design, Synthesis, DFT, and CAD methodology teams to define timing constraints, debug complex timing paths, and ensure zero-delay signoff readiness on advanced process nodes.
Key Responsibilities
Technical Leadership & Timing Signoff
• Constraints Management: Define, write, and validate complete SDC (Synopsys Design Constraints) for multi-mode, multi-corner (MCMM) timing views, including complex clock domain crossings (CDC) and false/multicycle paths.
• Full-Chip & Block STA: Lead block-level and full-chip timing closure, performing Static Timing Analysis across all process, voltage, and temperature (PVT) corners.
• Signal Integrity & Noise Analysis: Drive crosstalk analysis, glitched clock/data detection, noise analysis, and On-Chip Variation (OCV/AOCV/POCV) modeling.
• EOC & ECO Generation: Generate, validate, and integrate timing Engineering Change Orders (ECOs) using automated functional/leakage ECO techniques to achieve post-route timing closure without sacrificing area or power budget.
• Methodology & Flow Setup: Architect and optimize signoff STA methodology, script automation (Tcl/Python), and CAD flow integration for high-efficiency runtimes.
Cross-Functional Collaboration
• Work with the RTL & Architecture teams to resolve structural timing bottlenecks and critical path constraints early in the design cycle.
• Partner with Physical Design engineers to guide floorplanning, clock tree synthesis (CTS) strategies, and routing optimizations.
• Coordinate with DFT Engineers to set up and close timing for Scan, MBIST, and JTAG modes.
• Interface with EDA vendors to evaluate advanced STA tools and resolve tool/flow anomalies.
Required Qualifications
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, VLSI Design, or a related technical field.
• Experience: 8+ years of dedicated hands-on experience in Static Timing Analysis (STA) with a track record of multiple successful tape-outs on advanced nodes (7nm, 5nm, 3nm).
• Core STA Expertise:
o In-depth knowledge of MCMM timing analysis, AOCV/POCV, derating methodologies, signal integrity (crosstalk delta-delay and noise), and IR-drop impact on timing.
o Comprehensive understanding of complex clock topologies, clock domain crossings, and asynchronous interfaces.
o Proficient in manual and automated ECO flows (Hold/Setup fixes, leakage recovery).
• Tool Mastery:
o Synopsys: PrimeTime, PrimeTime-SI, PrimeTime-PX.
o Cadence: Tempus Timing Signoff Solution.
• Scripting: Advanced proficiency in Tcl and Python for flow development, reporting, and automated timing fix generation.
Show more Show less