XP

Lead Static Timing Analysis Engineer (STA)

Accepting applications

XQwave Pvt Ltd (Formerly Obsidian Solutions Pvt Ltd) · Chennai, Tamil Nadu, India

Full-Time Mid_senior ASICMentorPerlPythonRTL
Estimated market salary
₹30-55 LPA

This is a SiliconBoard market estimate, not an employer-posted salary.

Posted
2d ago
Category
Design
Experience
Mid_senior
Country
India
About the Company


We are looking for an experienced STA Lead with strong expertise in Static Timing Analysis and timing closure for complex ASIC/SoC designs.


About the Role


We are looking for an experienced STA Lead with strong expertise in Static Timing Analysis and timing closure for complex ASIC/SoC designs.


Responsibilities


Lead block-level and full-chip STA activities.
Develop and review SDC constraints.
Handle setup, hold, recovery and removal analysis.
Perform MMMC timing analysis across multiple PVT corners.
Work on OCV, AOCV, POCV, SI and crosstalk analysis.
Debug critical timing paths and drive timing closure.
Review false paths, multicycle paths and generated clock constraints.
Work closely with RTL, synthesis and physical design teams.
Support ECO generation and final timing sign-off.
Mentor junior engineers and drive STA deliverables.


Qualifications


Strong hands-on experience with Synopsys PrimeTime.
Expertise in STA, timing closure and SDC.
Good knowledge of MMMC, OCV/AOCV/POCV and SI analysis.
Experience with block and full-chip timing sign-off.
Strong understanding of ASIC design flow and physical design.
Good scripting skills in Tcl/Perl/Python.
Strong debugging, communication and team leadership skills.


Required Skills


Strong hands-on experience with Synopsys PrimeTime.
Expertise in STA, timing closure and SDC.
Good knowledge of MMMC, OCV/AOCV/POCV and SI analysis.
Experience with block and full-chip timing sign-off.
Strong understanding of ASIC design flow and physical design.
Good scripting skills in Tcl/Perl/Python.
Strong debugging, communication and team leadership skills.


Preferred Skills


Strong hands-on experience with Synopsys PrimeTime.
Expertise in STA, timing closure and SDC.
Good knowledge of MMMC, OCV/AOCV/POCV and SI analysis.
Experience with block and full-chip timing sign-off.
Strong understanding of ASIC design flow and physical design.
Good scripting skills in Tcl/Perl/Python.
Strong debugging, communication and team leadership skills.

Location

Chennai and Malaysia


Equal Opportunity Statement


We are committed to diversity and inclusivity.

Show more Show less