Lead SoC Design Engineer

Lead SoC Design Engineer - Stealth Startup - San Francisco Bay Area

We have partnered with a well-funded, stealth-mode technology company developing a next-generation computing platform built around a custom, high-performance edge SoC.

Joining as one of the first hardware hires, you'll be responsible for setting technical direction for the design of a high-performance edge-AI SoC, alongside building a team and leading to first tapeout.

You’ll also play a key role in defining the microarchitecture, making critical PPA trade-offs and leading the RTL implementation of key SoC subsystems.

What You’ll Do
Define and document detailed SoC microarchitecture and work closely with architecture, software and verification teams.
Drive performance, power and area (PPA) trade-offs to meet demanding product targets.
Lead RTL development for key SoC subsystems using Verilog/SystemVerilog.
Work with verification teams on test plans, emulation and first-pass silicon success.
Own key design-quality activities including Lint, CDC, RDC, SDC and VCLP.
Ensure designs can successfully progress through physical implementation while meeting frequency and power targets.

What We’re Looking For
10+ years’ experience developing complex ASICs, ideally on advanced process nodes.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or equivalent experience.
Strong knowledge of AMBA protocols, particularly AXI, AXI-S and APB.
Strong Verilog/SystemVerilog skills, including SVA.
Familiarity with the ARM ecosystem and/or cache-coherency protocols.
Experience designing SoCs with multiple power domains and UPF.

This is a flexible role based in the San Francisco Bay Area. Although hybrid is preferred, there is openness to remote work from across the US with occasional travel into the Bay Area.

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