Lead RTL Engineer

We are a premium talent solutions firm specializing in deep-tech, silicon design, and advanced engineering sectors. We bridge the gap between world-class engineering talent and forward-thinking companies.
Are you an elite, hands-on RTL expert who has steered silicon all the way through to a successful tapeout? Do you thrive at the intersection of high-level architecture and physical implementation?
We are scouting a powerhouse Lead RTL Engineer for one of our premier clients in Bangalore. The architect defines what gets built—you will own how it gets built.
### The Role at a Glance
This is a highly visible, hands-on leadership role. You will be the technical anchor bridging the gap between internal architecture and external design partners, owning every single milestone from RTL freeze to final GDSII handoff. Concurrently, you’ll build, mentor, and scale a top-tier team of 5–7 RTL engineers.
### What You’ll Do:
Execute & Lead: Drive the full design cycle while remaining hands-on—writing RTL, conducting rigorous code reviews, and running synthesis.
Set Standards: Define elite RTL coding standards, linting rules, and design methodologies.
Own Timing & Synthesis: Drive the synthesis flow (Design Compiler/Genus) and systematically achieve timing closure while managing SDC constraints.
Collaborate: Partner closely with verification teams to crush bugs and secure comprehensive coverage closure.
### What We Are Looking For:
Experience: 7+ years of deep RTL design experience using SystemVerilog.
Tapeout Proven: At least 1 successful tapeout through to GDSII—you know the realities of the full flow, not just the front-end.
Tool Mastery: Hands-on experience with synthesis and timing closure tools (Design Compiler, Genus, PrimeTime, or Tempus).
Domain Depth: Background in processor, DSP, or datapath-heavy designs utilizing advanced process nodes (28nm or below).
Code Hawk: Exceptional ability to spot timing hazards, FSM flaws, and non-synthesizable patterns during reviews.
### Bonus Points For:
Experience with VLIW or vector processor designs.
Knowledge of deterministic/real-time architectures (fixed latencies, no caches).
Competence in formal verification (SVA) or FPGA prototyping (Vivado).
Why Apply Through Taglynk?
At Taglynk, we match exceptional engineering talent with companies pushing the boundaries of deep tech. This role offers true ownership, an elite technical playground, and a fast track to shaping next-generation silicon.
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