SI
Lead RTL Design Engineer, IP Development
Accepting applicationsSynopsys Inc · Bengaluru, Karnataka, India
Full-Time Mid_senior AIASICDDREthernetPCIe
Posted
29 May
Category
Design
Experience
Mid_senior
Country
India
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent a decade building RTL that ships in silicon, not just passes verification, and you understand that the difference between a design that works and one that works at 1GHz across process corners is in the decisions you make when writing the architecture doc. You think in state machines, clock domains, and timing paths. When someone mentions a protocol spec, you do not just read it, you find the edge cases and the places where implementation will get messy.
You have architected control paths that actually hold together under synthesis. Asynchronous FIFOs, DMA engines, dual-port RAM interfaces, these are things you have debugged when CDC violations showed up in the reports. You know what it takes to close timing on a 600MHz design, and you have probably spent time in Fusion Compiler making it happen.
What You'll Be Doing
Architect and implement RTL for next-generation high-speed Ethernet IP cores, 100G and beyond, targeting Enterprise, Commercial, and Automotive applications
Translate protocol specifications including Ultra Accelerator Link, Ethernet, DDR, PCIe, or USB into detailed micro-architecture and design documentation
Own the full design flow from RTL coding through synthesis, CDC analysis, formal verification, and debug
Lead design tasks as an individual contributor and technical guide, mentoring designers on architecture decisions and design quality
Collaborate with global verification teams on test planning, coverage strategies, and verification closure
Drive P&R-aware synthesis for designs targeting 600MHz and above using tools like Fusion Compiler to close timing
The Impact You Will Have
Your architectures will power the DesignWare IP portfolio used by semiconductor companies worldwide to build next-generation systems
The control path designs you create will become reusable building blocks across multiple IP families, reducing time-to-market
Your technical leadership will raise the design quality bar across the Bangalore IP team
The high-speed Ethernet IP you deliver will enable customers to meet aggressive performance and power targets in data center, automotive, and edge computing applications
Your synthesis and timing closure work will set the standard for how the team approaches physical design challenges on advanced process nodes
What You'll Need
Bachelor's or Master's in Electrical Engineering with 10+ years of hands-on ASIC digital design experience
Deep knowledge of at least one industry protocol: Ultra Accelerator Link, Ethernet, DDR, PCIe, or USB
Proven experience architecting control path logic including asynchronous FIFOs, DMA architectures, and SPRAM/DPRAM interfaces
Strong command of synthesizable Verilog or SystemVerilog RTL coding with experience across lint, CDC, synthesis, formal checking, and static timing analysis
Hands-on experience closing timing on designs running at 600MHz or higher, experience with Fusion Compiler is a significant plus
Proficiency with Perforce and scripting in Perl or Shell, prior experience leading or mentoring designers is a major plus
Who You Are
You can explain a complex timing closure problem to a verification engineer in two sentences without losing the technical nuance
When a design review surfaces a potential issue, you ask the right questions rather than defending the architecture
You have debugged enough CDC violations to know which ones are benign and which ones will bite you in bring-up
You are comfortable working across time zones with distributed teams and know how to keep projects moving without constant meetings
You take ownership of quality, not just functionality, if the code is unmaintainable, you consider that a problem worth solving
The Team You'll Be Part Of
You will join the DesignWare IP Design R&D team at the Bangalore Design Center, working on synthesizable IP cores that ship to customers across commercial, enterprise, and automotive markets. This is a global team of expert engineers spread across multiple sites, and you will collaborate closely with RTL designers, verification engineers, and customers on technically challenging IP development.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Show more Show less
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent a decade building RTL that ships in silicon, not just passes verification, and you understand that the difference between a design that works and one that works at 1GHz across process corners is in the decisions you make when writing the architecture doc. You think in state machines, clock domains, and timing paths. When someone mentions a protocol spec, you do not just read it, you find the edge cases and the places where implementation will get messy.
You have architected control paths that actually hold together under synthesis. Asynchronous FIFOs, DMA engines, dual-port RAM interfaces, these are things you have debugged when CDC violations showed up in the reports. You know what it takes to close timing on a 600MHz design, and you have probably spent time in Fusion Compiler making it happen.
What You'll Be Doing
Architect and implement RTL for next-generation high-speed Ethernet IP cores, 100G and beyond, targeting Enterprise, Commercial, and Automotive applications
Translate protocol specifications including Ultra Accelerator Link, Ethernet, DDR, PCIe, or USB into detailed micro-architecture and design documentation
Own the full design flow from RTL coding through synthesis, CDC analysis, formal verification, and debug
Lead design tasks as an individual contributor and technical guide, mentoring designers on architecture decisions and design quality
Collaborate with global verification teams on test planning, coverage strategies, and verification closure
Drive P&R-aware synthesis for designs targeting 600MHz and above using tools like Fusion Compiler to close timing
The Impact You Will Have
Your architectures will power the DesignWare IP portfolio used by semiconductor companies worldwide to build next-generation systems
The control path designs you create will become reusable building blocks across multiple IP families, reducing time-to-market
Your technical leadership will raise the design quality bar across the Bangalore IP team
The high-speed Ethernet IP you deliver will enable customers to meet aggressive performance and power targets in data center, automotive, and edge computing applications
Your synthesis and timing closure work will set the standard for how the team approaches physical design challenges on advanced process nodes
What You'll Need
Bachelor's or Master's in Electrical Engineering with 10+ years of hands-on ASIC digital design experience
Deep knowledge of at least one industry protocol: Ultra Accelerator Link, Ethernet, DDR, PCIe, or USB
Proven experience architecting control path logic including asynchronous FIFOs, DMA architectures, and SPRAM/DPRAM interfaces
Strong command of synthesizable Verilog or SystemVerilog RTL coding with experience across lint, CDC, synthesis, formal checking, and static timing analysis
Hands-on experience closing timing on designs running at 600MHz or higher, experience with Fusion Compiler is a significant plus
Proficiency with Perforce and scripting in Perl or Shell, prior experience leading or mentoring designers is a major plus
Who You Are
You can explain a complex timing closure problem to a verification engineer in two sentences without losing the technical nuance
When a design review surfaces a potential issue, you ask the right questions rather than defending the architecture
You have debugged enough CDC violations to know which ones are benign and which ones will bite you in bring-up
You are comfortable working across time zones with distributed teams and know how to keep projects moving without constant meetings
You take ownership of quality, not just functionality, if the code is unmaintainable, you consider that a problem worth solving
The Team You'll Be Part Of
You will join the DesignWare IP Design R&D team at the Bangalore Design Center, working on synthesizable IP cores that ship to customers across commercial, enterprise, and automotive markets. This is a global team of expert engineers spread across multiple sites, and you will collaborate closely with RTL designers, verification engineers, and customers on technically challenging IP development.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Show more Show less