Lead - RTL Design Engineer

Member Technical Staff / Principal RTL Design Engineer – 10+ Years
Define RTL architecture and design strategy for complex SoCs
Own SoC-level integration, clocks, resets, and power intent
Review and sign off RTL quality, lint/CDC, and low-power readiness
Drive RTL methodologies, coding guidelines, and best practices
Mentor RTL engineers and provide technical leadership
Interface with customers and cross-functional stakeholders

Tools & Skills
Languages: Verilog, SystemVerilog
Checks: Lint, CDC/RDC, LEC
Synthesis Awareness: Design Compiler, Genus
Low Power: UPF/CPF
Protocols: AMBA (AXI/AHB/APB), SPI, I2C, UART (as applicable)
Scripting: Tcl, Python, Shell
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