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Lead/Principal Circuit Design - IO PHY
Accepting applicationsCadence · Hyderabad, Telangana, India
Full-Time Mid_senior AnalogCadenceMatlabPCIeSERDES
Estimated market salary
₹41-73 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
22h ago
Category
Design
Experience
Mid_senior
Country
India
About the Company
Cadence Hyderabad is Hiring for Lead/Principal Circuit Design - IO PHY
About the Role
The role involves leading the design of High Speed IO PHY Interfaces and requires a strong technical background in circuit design.
Responsibilities
Education Qualification: B.Tech / M.Tech Degree from prestigious college.
6-15 years of strong technical experience in Circuit design of High Speed IO PHY Interfaces like PCIe SERDES, DDRIO PHY, HBMIO, UCIe IO, MIPI, USB etc.
Strong knowledge of architectures and circuits of Transmitter, Receiver, Clocking and Power Delivery Systems and blocks is must.
Must be aware and working knowledge of PHY Level Signal Integrity Analysis, Training and Calibration, Post-Silicon Qualification of PHY functionality, Design and Testability of the IO Link, Power Integrity, Analog Signal Routing Integrity and Signoff etc.
Should know about lib generation of Analog macros, generating current and timing models of macro blocks.
Knowledge and work in Real Value Behavioral models of Analog blocks will be a great advantage.
Experience in System modelling to build High Speed PHY system design / test in Matlab, AMS Verilog or any other tool is required to be considered for Architect position.
Post-Silicon Testing exposure is desired for Senior designers and Architects.
All designers should be well aware about layout design requirements and impact, reliability (ESD, EMIR etc) requirements and exposure to Analog models like .libs, Verilog models will be a plus.
The candidate should have good communication skills and a team player to work in global teams.
Qualifications
B.Tech / M.Tech Degree from prestigious college.
Required Skills
Strong technical experience in Circuit design of High Speed IO PHY Interfaces.
Knowledge of architectures and circuits of Transmitter, Receiver, Clocking and Power Delivery Systems.
Working knowledge of PHY Level Signal Integrity Analysis, Training and Calibration.
Design and Testability of the IO Link, Power Integrity, Analog Signal Routing Integrity.
Good communication skills and ability to work in global teams.
Preferred Skills
Knowledge and work in Real Value Behavioral models of Analog blocks.
Experience in System modelling to build High Speed PHY system design / test in Matlab, AMS Verilog or any other tool.
Post-Silicon Testing exposure.
Exposure to Analog models like .libs, Verilog models.
Show more Show less
Cadence Hyderabad is Hiring for Lead/Principal Circuit Design - IO PHY
About the Role
The role involves leading the design of High Speed IO PHY Interfaces and requires a strong technical background in circuit design.
Responsibilities
Education Qualification: B.Tech / M.Tech Degree from prestigious college.
6-15 years of strong technical experience in Circuit design of High Speed IO PHY Interfaces like PCIe SERDES, DDRIO PHY, HBMIO, UCIe IO, MIPI, USB etc.
Strong knowledge of architectures and circuits of Transmitter, Receiver, Clocking and Power Delivery Systems and blocks is must.
Must be aware and working knowledge of PHY Level Signal Integrity Analysis, Training and Calibration, Post-Silicon Qualification of PHY functionality, Design and Testability of the IO Link, Power Integrity, Analog Signal Routing Integrity and Signoff etc.
Should know about lib generation of Analog macros, generating current and timing models of macro blocks.
Knowledge and work in Real Value Behavioral models of Analog blocks will be a great advantage.
Experience in System modelling to build High Speed PHY system design / test in Matlab, AMS Verilog or any other tool is required to be considered for Architect position.
Post-Silicon Testing exposure is desired for Senior designers and Architects.
All designers should be well aware about layout design requirements and impact, reliability (ESD, EMIR etc) requirements and exposure to Analog models like .libs, Verilog models will be a plus.
The candidate should have good communication skills and a team player to work in global teams.
Qualifications
B.Tech / M.Tech Degree from prestigious college.
Required Skills
Strong technical experience in Circuit design of High Speed IO PHY Interfaces.
Knowledge of architectures and circuits of Transmitter, Receiver, Clocking and Power Delivery Systems.
Working knowledge of PHY Level Signal Integrity Analysis, Training and Calibration.
Design and Testability of the IO Link, Power Integrity, Analog Signal Routing Integrity.
Good communication skills and ability to work in global teams.
Preferred Skills
Knowledge and work in Real Value Behavioral models of Analog blocks.
Experience in System modelling to build High Speed PHY system design / test in Matlab, AMS Verilog or any other tool.
Post-Silicon Testing exposure.
Exposure to Analog models like .libs, Verilog models.
Show more Show less