Lead Physical Design Engineer – EM/IR Signoff

Lead Physical Design Engineer – EM/IR Signoff
Location: Bengaluru
Experience: 6–10 Years
Role Overview
We are looking for Lead Physical Design Engineer with deep expertise in EM/IR analysis and signoff for advanced-node SoC designs. The ideal candidate will drive power integrity closure, identify reliability risks, and collaborate across implementation, package, and technology teams to achieve first-pass silicon success.
Key Responsibilities
Lead EM/IR analysis, debugging, and closure for complex SoC/block-level designs.
Perform static and dynamic IR-drop analysis and electromigration signoff across advanced technology nodes.
Develop and optimize power grid architectures, power delivery networks (PDN), and decoupling strategies.
Analyze power integrity issues and drive fixes through floorplan, placement, routing, and power network enhancements.
Collaborate with Physical Design, STA, Package, Power, and Foundry teams to ensure robust signoff.
Drive methodology improvements, automation, and flow enhancements for EM/IR convergence.
Technical Requirements
6–10 years of hands-on Physical Design experience with strong focus on EM/IR signoff.
Expertise in industry-standard tools such as Ansys RedHawk, Cadence Voltus, or equivalent.
Strong understanding of power integrity, power grid design, voltage drop analysis, electromigration, and reliability concepts.
Experience with advanced-node technologies (16nm/7nm/5nm and below).
Solid knowledge of floorplanning, placement, CTS, routing, extraction, and physical signoff flows.
Proficiency in Tcl, Python, and Unix/Linux scripting for automation.
Strong debugging, analytical, and problem-solving skills.
Preferred
Experience with high-performance CPU, GPU, AI/ML, Networking, or Datacenter SoCs.
Exposure to package-aware power integrity analysis and silicon correlation.
If you are passionate about solving complex power integrity challenges and driving signoff closure for cutting-edge semiconductor products, we'd like to hear from you.
Show more Show less