SP
"Lead Physical Design Engineer"
Accepting applicationsSiMaxTech Pvt Ltd · Greater Bengaluru Area
Full-Time Mid_senior Cadence InnovusRTL-to-GDSIISTATiming ClosurePhysical Design
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
India
Job Title: Lead Physical Design Engineer
Experience: 7–12 Years
Location: Bangalore
Employment Type: Full-Time
Job Summary:
SiMaxTech is looking for an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus to drive the complete RTL-to-GDSII implementation flow for complex SoCs. The ideal candidate should have hands-on experience in advanced technology nodes, timing closure, physical verification, and mentoring engineering teams while ensuring high-quality tape-outs.
Key Responsibilities
Lead end-to-end Physical Design implementation from Netlist to GDSII.
Perform Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Optimization using Cadence Innovus.
Drive timing closure across all PVT corners using Tempus/PrimeTime.
Perform congestion analysis and optimize Power, Performance, and Area (PPA).
Resolve setup/hold violations and execute ECO implementation.
Perform Physical Verification including DRC, LVS, Antenna, and Density checks.
Work on IR Drop and EM analysis using Voltus/RedHawk.
Collaborate with RTL, DFT, STA, Verification, and Packaging teams for successful tape-outs.
Develop automation scripts using Tcl, Perl, Python, or Shell.
Mentor junior engineers and review design quality.
Support multiple project tape-outs while ensuring schedule adherence and design quality
Regards,
Sruthi
Mail Id: sai.sruthi@si-maxtech.com
Show more Show less
Experience: 7–12 Years
Location: Bangalore
Employment Type: Full-Time
Job Summary:
SiMaxTech is looking for an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus to drive the complete RTL-to-GDSII implementation flow for complex SoCs. The ideal candidate should have hands-on experience in advanced technology nodes, timing closure, physical verification, and mentoring engineering teams while ensuring high-quality tape-outs.
Key Responsibilities
Lead end-to-end Physical Design implementation from Netlist to GDSII.
Perform Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Optimization using Cadence Innovus.
Drive timing closure across all PVT corners using Tempus/PrimeTime.
Perform congestion analysis and optimize Power, Performance, and Area (PPA).
Resolve setup/hold violations and execute ECO implementation.
Perform Physical Verification including DRC, LVS, Antenna, and Density checks.
Work on IR Drop and EM analysis using Voltus/RedHawk.
Collaborate with RTL, DFT, STA, Verification, and Packaging teams for successful tape-outs.
Develop automation scripts using Tcl, Perl, Python, or Shell.
Mentor junior engineers and review design quality.
Support multiple project tape-outs while ensuring schedule adherence and design quality
Regards,
Sruthi
Mail Id: sai.sruthi@si-maxtech.com
Show more Show less
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