NS

Lead Physical Design Engineer

Accepting applications

NXP Semiconductors · Pune Division, Maharashtra, India

Full-Time Mid_senior CadenceDFTInnovusPerlPython
Estimated market salary
₹33-59 LPA

This is a SiliconBoard market estimate, not an employer-posted salary.

Posted
15 Jun
Category
Design
Experience
Mid_senior
Country
India
Job Summary

We are seeking a highly experienced PDN Engineer for iMCU & Connectivity to lead and contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits. This role involves driving technical solutions, mentoring junior engineers, and ensuring the timely delivery of cutting-edge products within NXP's diverse portfolio.

Job Responsibilities

As a PD Engineer, your responsibilities will include but are not limited to:

Conduct power integrity (IR drop), SNA and EM on top-level.
Will be responsible for floor planning, power grid design, place and route, low power implementation, clock tree synthesis, timing closure, power/signal integrity analysis, to physical verification (DRC/LVS/Antenna).
The role would involve in-depth knowledge and responsibilities spanning all aspects of physical implementation.
Drive the definition and implementation of physical design methodologies, flows, and best practices to optimize performance, power, and area.
Perform comprehensive static timing analysis (STA) and ensure all timing constraints are met across various corners and modes.
Collaborate closely with architecture, RTL design, DFT, and package teams to ensure seamless integration and successful product delivery.
Evaluate and adopt new EDA tools and technologies to improve design efficiency and quality.

Job Qualifications

Bachelor's degree with 9+ years of professional experience or Master's degree with 8+ years of professional experience.
Working knowledge on advance tech nodes 16ff and below is highly desirable.
Extensive knowledge and experience in back-end implementation tasks such as low power implementation, PDN and power analysis.
Expert-level proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, Ansys RedHawk/PowerSI).
Strong knowledge of power analysis and optimisation techniques (e.g., UPF/CPF, clock gating, power intent).
Solid understanding of semiconductor device physics, process technology effects, and DFM/DFY considerations.
Proficiency in scripting languages (e.g., Tcl, Python, Perl) for automation of design flows and analysis.
Excellent problem-solving, analytical, and debugging skills.
Strong communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and mentor other engineers.
Ability to work independently and take ownership of critical design aspects.

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