Lead Physical Design Engineer

Lead Physical Design Engineer
Location: Bengaluru, India
Experience: 8–12+ Years
Role Overview
We are seeking a highly skilled Lead Physical Design Engineer to drive planning, execution, and closure of multiple complex ASIC/SoC blocks. The ideal candidate will have strong hands-on expertise in block-level implementation and signoff across advanced technology nodes.
Responsibilities
Own end-to-end execution and closure of multiple highly complex blocks with challenging congestion and timing requirements.
Drive block-level floorplanning, placement, CTS, routing, ECO implementation, and QoR optimization using Cadence Innovus.
Lead timing closure activities including Setup/Hold optimization, MMMC analysis, constraints/exceptions management, and QoR improvement.
Debug congestion and routability issues through macro placement, pin access optimization, blockages, and density management.
Ensure signoff readiness including DRC/LVS closure, SI-aware optimization, and IR/EM convergence.
Define and track block-level metrics and drive closure actions to meet schedule and quality targets.
Collaborate closely with STA, DFT, Synthesis, and CAD teams to ensure smooth tapeout execution.
Requirements
8–12+ years of ASIC/SoC Physical Design experience with multiple successful tapeouts.
Strong hands-on expertise in Cadence Innovus for block-level implementation.
Experience with advanced nodes (2nm/3nm/4nm/6nm) and mature technologies.
Solid understanding of MMMC, SI, IR/EM, DRC/LVS signoff methodologies.
Proficiency in Tcl scripting (mandatory); Python, Perl, and Shell scripting are preferred.
Excellent debugging, cross-functional collaboration, and communication skills.
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