P
Lead DFT Engineer
Accepting applicationsProxelera · Hyderabad, Telangana, India
Full-Time Mid_senior ATPGCadenceDFTGenusSynopsys
Estimated market salary
₹71-128 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Test
Experience
Mid_senior
Country
India
Proxelera is India’s premium chip and system software product engineering partner. Our engineers take extreme passion in your assignments and deliver through their years of high quality experience to make your product successful. We understand the challenges of all aspects of product engineering – right from design planning stage to post silicon work. We also offer you unparalleled quality of service in productization of your chip through reference system design and system software development.
Job Descriptio
n:Job Title: DFT Lead Engineer - 8-12Y
rsNo. Of Positions:
5Work Location: Bangalo
re
Key Skills Requir
ed:DFT Lead ( Bangalore / Hyderab
ad)Key Requiremen
ts:Proven experience as a DFT (Design for Test) L
eadStrong expertise in Synopsys DFT to
olsMust have hands-on experience in TetraMAX (ATPG to
ol)Experience
in:Scan insertion and compression techniq
uesATPG pattern generation and coverage analy
sisAbility to lead and mentor a t
eam
DFT Engineer & Lead ( Bangal
ore)Key Requireme
nts:Strong experience in DFT implementation and valida
tionMandatory expertise in Cadence to
ols:Modus (DFT solut
ion)Genus (synthesis t
ool)Xcelium (simulation t
ool)Experience
in:Scan architecture de
signATPG and fault coverage anal
ysisHands-on involvement in end-to-end DFT
flowAbility to handle DFT planning and execu
tionFor Lead r
ole:Team handling and stakeholder management experi
ence
Show more Show less
Job Descriptio
n:Job Title: DFT Lead Engineer - 8-12Y
rsNo. Of Positions:
5Work Location: Bangalo
re
Key Skills Requir
ed:DFT Lead ( Bangalore / Hyderab
ad)Key Requiremen
ts:Proven experience as a DFT (Design for Test) L
eadStrong expertise in Synopsys DFT to
olsMust have hands-on experience in TetraMAX (ATPG to
ol)Experience
in:Scan insertion and compression techniq
uesATPG pattern generation and coverage analy
sisAbility to lead and mentor a t
eam
DFT Engineer & Lead ( Bangal
ore)Key Requireme
nts:Strong experience in DFT implementation and valida
tionMandatory expertise in Cadence to
ols:Modus (DFT solut
ion)Genus (synthesis t
ool)Xcelium (simulation t
ool)Experience
in:Scan architecture de
signATPG and fault coverage anal
ysisHands-on involvement in end-to-end DFT
flowAbility to handle DFT planning and execu
tionFor Lead r
ole:Team handling and stakeholder management experi
ence
Show more Show less
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