SP
Lead Design Verification Engineer-DFX
Accepting applicationsSilicon Patterns · Bengaluru, Karnataka, India
Full-Time Mid_senior AIATPGBoundary scanCadenceDDR
Estimated market salary
₹27-49 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Verification
Experience
Mid_senior
Country
India
Lead Design Verification (DV) / DFX Engineer
Company: Silicon Patterns
Location: Bengaluru
Experience: 5+ Years
Employment Type: Full-Time
Job Summary
Silicon Patterns is seeking an experienced DV-DFX Engineer to contribute to the verification and Design-for-X (DFX) implementation of complex SoCs/IPs. The ideal candidate will have strong expertise in SystemVerilog/UVM-based verification methodologies and hands-on experience in DFT/DFX architectures, ensuring high-quality silicon delivery and first-pass silicon success.
Key Responsibilities
Develop and execute comprehensive verification plans for SoC/IP subsystems.
Build and maintain reusable verification environments using SystemVerilog and UVM.
Develop testbenches, assertions, scoreboards, functional coverage, and regression suites.
Verify high-speed interfaces such as PCIe, DDR, Ethernet, CXL, AXI, AHB, and APB.
Collaborate with RTL, Architecture, DFT, Physical Design, and Validation teams.
Define and implement DFX strategies including:
Design for Testability (DFT)
Scan insertion and scan verification
MBIST/LBIST verification
JTAG/TAP controller validation
Boundary scan verification
ATPG support and coverage analysis
Perform debug and root-cause analysis using simulation waveforms and logs.
Drive coverage closure and verification sign-off activities.
Participate in code reviews, methodology improvements, and verification planning.
Required Skills
5+ years of experience in Design Verification.
Strong knowledge of:
SystemVerilog
UVM
Verilog
Assertions (SVA)
Functional Coverage
Experience with simulation tools:
Synopsys VCS
Cadence Xcelium
Siemens Questa
Hands-on experience in DFX/DFT verification:
Scan
MBIST
LBIST
JTAG
ATPG concepts
Strong debugging and verification closure skills.
Good understanding of digital design and computer architecture concepts.
Experience with scripting languages:
Python
Perl
TCL
Shell scripting
Preferred Qualifications
Experience in SoC-level verification.
Knowledge of Formal Verification methodologies.
Exposure to Emulation/FPGA prototyping.
Familiarity with low-power verification (UPF/CPF).
Experience in AI/ML, Automotive, Networking, or High-Performance Computing SoCs.
Educational Qualification
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Embedded Systems, or related fields.
What You'll Bring
Strong problem-solving and debugging skills.
Ability to work independently and lead verification tasks.
Excellent communication and cross-functional collaboration skills.
Passion for delivering high-quality silicon products.
Show more Show less
Company: Silicon Patterns
Location: Bengaluru
Experience: 5+ Years
Employment Type: Full-Time
Job Summary
Silicon Patterns is seeking an experienced DV-DFX Engineer to contribute to the verification and Design-for-X (DFX) implementation of complex SoCs/IPs. The ideal candidate will have strong expertise in SystemVerilog/UVM-based verification methodologies and hands-on experience in DFT/DFX architectures, ensuring high-quality silicon delivery and first-pass silicon success.
Key Responsibilities
Develop and execute comprehensive verification plans for SoC/IP subsystems.
Build and maintain reusable verification environments using SystemVerilog and UVM.
Develop testbenches, assertions, scoreboards, functional coverage, and regression suites.
Verify high-speed interfaces such as PCIe, DDR, Ethernet, CXL, AXI, AHB, and APB.
Collaborate with RTL, Architecture, DFT, Physical Design, and Validation teams.
Define and implement DFX strategies including:
Design for Testability (DFT)
Scan insertion and scan verification
MBIST/LBIST verification
JTAG/TAP controller validation
Boundary scan verification
ATPG support and coverage analysis
Perform debug and root-cause analysis using simulation waveforms and logs.
Drive coverage closure and verification sign-off activities.
Participate in code reviews, methodology improvements, and verification planning.
Required Skills
5+ years of experience in Design Verification.
Strong knowledge of:
SystemVerilog
UVM
Verilog
Assertions (SVA)
Functional Coverage
Experience with simulation tools:
Synopsys VCS
Cadence Xcelium
Siemens Questa
Hands-on experience in DFX/DFT verification:
Scan
MBIST
LBIST
JTAG
ATPG concepts
Strong debugging and verification closure skills.
Good understanding of digital design and computer architecture concepts.
Experience with scripting languages:
Python
Perl
TCL
Shell scripting
Preferred Qualifications
Experience in SoC-level verification.
Knowledge of Formal Verification methodologies.
Exposure to Emulation/FPGA prototyping.
Familiarity with low-power verification (UPF/CPF).
Experience in AI/ML, Automotive, Networking, or High-Performance Computing SoCs.
Educational Qualification
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Embedded Systems, or related fields.
What You'll Bring
Strong problem-solving and debugging skills.
Ability to work independently and lead verification tasks.
Excellent communication and cross-functional collaboration skills.
Passion for delivering high-quality silicon products.
Show more Show less