Lead Design Verification Engineer

Lead Design Verification Engineer
Location: Bengaluru
Experience: 6–12 Years

Role Overview
LeadSoc Technologies is seeking a highly skilled Lead Design Verification Engineer to drive verification of next-generation SoC/IP designs. The ideal candidate will possess deep expertise in high-speed protocols, RISC-V architecture, computer architecture concepts, and advanced SystemVerilog/UVM-based verification methodologies.
Key Responsibilities
Lead verification activities for complex SoC, subsystem, and IP-level designs from specification to tape-out.
Develop comprehensive verification plans, testbench architectures, coverage models, and verification strategies.
Build and maintain scalable verification environments using SystemVerilog and UVM.
Verify RISC-V processor cores, cache subsystems, interconnects, and SoC fabrics.
Develop constrained-random, directed, and scenario-based test suites to achieve coverage closure.
Perform protocol compliance and interoperability verification for high-speed interfaces such as PCIe, USB, Ethernet, DDR, CXL, AXI, CHI, and AMBA-based protocols.
Drive functional, code, assertion, and formal coverage closure.
Develop checkers, scoreboards, assertions (SVA), and performance validation frameworks.
Analyze simulation failures, debug RTL issues, and collaborate closely with architecture, design, firmware, and physical design teams.
Mentor junior verification engineers and provide technical leadership across projects.
Required Skills & Experience
6–12 years of hands-on Design Verification experience in semiconductor/VLSI product development.
Strong expertise in SystemVerilog, UVM, Assertions (SVA), and verification methodologies.
Solid understanding of RISC-V ISA, processor pipelines, cache coherency, memory hierarchy, interrupts, and privilege architecture.
Strong computer architecture fundamentals including CPUs, MMU, cache subsystems, interconnects, and performance analysis.
Extensive verification experience with one or more high-speed protocols:
PCIe (Gen5/Gen6 preferred)
DDR4/DDR5/LPDDR
USB 3.x/USB4
Ethernet
CXL
AXI/ACE/CHI
Experience in developing reusable VIPs, protocol checkers, scoreboards, and coverage models.
Strong debugging skills using industry-standard simulators and waveform analysis tools.
Proficiency in scripting using Python, Perl, or Shell scripting.
Experience with emulation, formal verification, or post-silicon validation is a plus.
Preferred Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
Experience leading verification teams and driving project execution independently.
Strong communication, problem-solving, and technical leadership skills.
What You'll Work On
High-performance RISC-V SoCs
Advanced CPU and subsystem verification
High-speed protocol IPs and interconnects
Next-generation semiconductor products targeting data center, AI, networking, and embedded applications
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