Lead Design Verification Engineer

Company Description Incise Infotech Limited (Incise Infotech Pvt Ltd) is a technology company specializing in semiconductor design services, semiconductor product development, and IT products for sectors such as banking and vehicle tracking. The company’s semiconductor expertise spans SoC and IP verification, RTL design, virtual prototyping, physical design, DFT, analog mixed-signal, memory and I/O design, and FPGA-based solutions. Incise also delivers software development and IT services, including .NET, Java, PHP, Android, iOS development, and Oracle database administration. By bringing together top global talent, Incise aims to architect next-generation semiconductor SoCs and software solutions with “right first time” quality. The organization focuses on innovation, collaboration, and best practices to simplify and enhance everyday life through advanced technology.


Role Description This is a full-time, on-site role for a Lead Design Verification Engineer based in Bangalore. The person in this role will lead verification efforts for complex SoC and IP designs, including planning, developing, and executing verification strategies and test plans. Day-to-day responsibilities include driving functional and formal verification, creating and reviewing testbench architectures, writing and debugging test cases, and ensuring thorough coverage closure. The Lead Design Verification Engineer will collaborate closely with RTL design, architecture, and validation teams to identify and resolve design issues, participate in design and code reviews, and provide technical guidance to junior engineers. The role also involves coordinating with project stakeholders, tracking verification progress against milestones, and contributing to continuous improvement of verification methodologies and best practices.
Qualifications
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
Strong expertise in Functional Verification and Debugging, with proven 5 to 8 years' experience leading verification of complex digital designs in IPs or SoCs.
Hands-on experience with Formal Verification techniques and tools, including property specification and formal test planning.
Solid background in RTL Design and Computer Architecture, with the ability to understand micro-architecture, interfaces, and performance trade-offs.
Proficiency in hardware description and verification languages (such as SystemVerilog, UVM/OVM), and familiarity with industry-standard EDA tools.
Experience in leading or mentoring verification teams, including task planning, code reviews, and technical coaching.
Strong analytical, problem-solving, and communication skills, with the ability to collaborate effectively in cross-functional engineering teams.
Experience in IP OR SoC-level verification, low-power verification, or high-speed interfaces is an advantage.
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