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Lead Design Verification Engineer
Accepting applicationsAsian Hires · Bengaluru, Karnataka, India
Full-Time Mid_senior AISoCSynopsysSystemVerilogUVM
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Verification
Experience
Mid_senior
Country
India
Experience: 10–17 Years
Position: 1
About the Role
We are looking for an experienced Lead Design Verification Engineer with strong expertise in IP-level design verification and hands-on experience with Verilog, SystemVerilog and UVM.
The ideal candidate should have strong testbench development capabilities, mastery of EDA verification tools such as VCS and Verdi, and exposure to system-level activities including VnC, SoC bring-up, GLS and firmware.
Exposure to AI tools, scripting/automation, and digital + analog verification will be an added advantage.
Top 3 Mandatory Skills
Verilog
SystemVerilog
UVM
Key Responsibilities
Develop and maintain IP-level verification testbench components.
Perform functional verification using Verilog, SystemVerilog and UVM.
Design, develop and debug verification environments and testbench components.
Work extensively with EDA tools including Synopsys VCS and Verdi.
Analyze simulation results, debug failures and identify root causes.
Collaborate with design and verification teams to achieve verification goals.
Contribute to system-level activities including VnC, SoC bring-up, GLS and firmware-related verification.
Develop scripts and automation solutions to improve verification efficiency.
Apply AI-assisted tools where relevant to improve development, debugging and verification workflows.
Work with teams across different geographies and communicate technical issues effectively.
Mandatory Requirements
10+ years of relevant Design Verification experience.
Strong hands-on experience with Verilog, SystemVerilog and UVM.
Strong IP-level testbench/component development experience.
Excellent knowledge of verification methodologies and flows.
Hands-on expertise with VCS and Verdi or equivalent EDA tools.
System-level exposure such as VnC, SoC bring-up, GLS and firmware.
Strong debugging and problem-solving skills.
Good communication skills and ability to collaborate with teams across geographies.
Good to Have
Scripting experience for verification automation.
Experience using AI tools in engineering/verification workflows.
Exposure to digital + analog verification.
Broader SoC-level verification experience.
Show more Show less
Position: 1
About the Role
We are looking for an experienced Lead Design Verification Engineer with strong expertise in IP-level design verification and hands-on experience with Verilog, SystemVerilog and UVM.
The ideal candidate should have strong testbench development capabilities, mastery of EDA verification tools such as VCS and Verdi, and exposure to system-level activities including VnC, SoC bring-up, GLS and firmware.
Exposure to AI tools, scripting/automation, and digital + analog verification will be an added advantage.
Top 3 Mandatory Skills
Verilog
SystemVerilog
UVM
Key Responsibilities
Develop and maintain IP-level verification testbench components.
Perform functional verification using Verilog, SystemVerilog and UVM.
Design, develop and debug verification environments and testbench components.
Work extensively with EDA tools including Synopsys VCS and Verdi.
Analyze simulation results, debug failures and identify root causes.
Collaborate with design and verification teams to achieve verification goals.
Contribute to system-level activities including VnC, SoC bring-up, GLS and firmware-related verification.
Develop scripts and automation solutions to improve verification efficiency.
Apply AI-assisted tools where relevant to improve development, debugging and verification workflows.
Work with teams across different geographies and communicate technical issues effectively.
Mandatory Requirements
10+ years of relevant Design Verification experience.
Strong hands-on experience with Verilog, SystemVerilog and UVM.
Strong IP-level testbench/component development experience.
Excellent knowledge of verification methodologies and flows.
Hands-on expertise with VCS and Verdi or equivalent EDA tools.
System-level exposure such as VnC, SoC bring-up, GLS and firmware.
Strong debugging and problem-solving skills.
Good communication skills and ability to collaborate with teams across geographies.
Good to Have
Scripting experience for verification automation.
Experience using AI tools in engineering/verification workflows.
Exposure to digital + analog verification.
Broader SoC-level verification experience.
Show more Show less