WA
Lead Design Verification
Accepting applicationsWeekday AI (YC W21) · Bengaluru, Karnataka, India
Full-Time Mid_senior SystemVerilogUVMSoCVerification
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
India
This role is for one of the Weekday's clients
Salary range: Rs 500000 - Rs 6000000 (ie INR 5 - 60 LPA)
Min Experience: 7+ years
Location: Bengaluru
JobType: full-time
We are looking for an experienced Lead Design Verification Engineer with 7-18 years of experience to drive the verification of complex digital and SoC designs. This role is ideal for professionals who have extensive expertise in verification methodologies and are passionate about building high-quality, reliable semiconductor products. As a technical leader, you will be responsible for defining verification strategies, developing reusable verification environments, mentoring engineering teams, and ensuring first-pass silicon success. The ideal candidate should possess deep knowledge of SystemVerilog, UVM, and DisplayPort verification, along with strong debugging and problem-solving capabilities.
Requirements
Key Responsibilities
Lead end-to-end verification activities for complex digital IPs, subsystems, and SoC designs
Develop comprehensive verification plans based on design specifications and functional requirements
Build scalable, reusable, and modular verification environments using SystemVerilog and UVM
Create constrained-random testbenches, assertions, scoreboards, functional coverage models, and verification components
Verify DisplayPort IPs and interfaces across multiple protocol versions and ensure compliance with industry standards
Collaborate closely with design, architecture, firmware, validation, and physical design teams throughout the development lifecycle
Perform simulation, debugging, root cause analysis, and issue resolution for functional failures
Drive coverage closure by monitoring functional, code, and assertion coverage metrics
Participate in design reviews, specification analysis, and architecture discussions to improve design quality and testability
Develop automation scripts to improve verification productivity and regression efficiency
Analyze protocol compliance, timing behavior, corner cases, and system-level interactions
Mentor junior verification engineers and provide technical guidance on verification best practices
Support post-silicon validation teams in debugging and resolving silicon issues when required
Required Qualifications
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related discipline
7-18 years of hands-on experience in Design Verification for ASIC, FPGA, or SoC development
Strong expertise in digital design verification methodologies and industry-standard verification flows
Excellent analytical, debugging, and communication skills
Experience leading verification teams or owning verification deliverables for complex projects is highly preferred
Must-Have Skills
Strong expertise in SystemVerilog for developing advanced verification environments
Extensive experience with UVM (Universal Verification Methodology) including reusable verification components, sequences, agents, scoreboards, and functional coverage
Hands-on experience verifying DisplayPort protocols and related interfaces
Expertise in constrained-random verification techniques and assertion-based verification
Experience with simulation, waveform debugging, regression management, and coverage-driven verification
Strong understanding of digital logic design, computer architecture, and hardware verification concepts
Experience with protocol verification, functional coverage, code coverage, and coverage closure
Familiarity with industry-standard EDA simulation and debugging tools
Good-to-Have Skills
Experience with additional high-speed protocols such as PCIe, USB, HDMI, MIPI, Ethernet, or DDR
Knowledge of scripting languages such as Python, Perl, Shell, or TCL for automation
Exposure to Formal Verification methodologies
Experience with emulation, FPGA prototyping, or hardware acceleration platforms
Understanding of low-power verification methodologies including UPF/CPF
Familiarity with CI/CD workflows for verification automation
Knowledge of SoC integration, AMBA protocols (AXI, AHB, APB), and embedded systems
Experience supporting post-silicon validation and debug activities
Show more Show less
Salary range: Rs 500000 - Rs 6000000 (ie INR 5 - 60 LPA)
Min Experience: 7+ years
Location: Bengaluru
JobType: full-time
We are looking for an experienced Lead Design Verification Engineer with 7-18 years of experience to drive the verification of complex digital and SoC designs. This role is ideal for professionals who have extensive expertise in verification methodologies and are passionate about building high-quality, reliable semiconductor products. As a technical leader, you will be responsible for defining verification strategies, developing reusable verification environments, mentoring engineering teams, and ensuring first-pass silicon success. The ideal candidate should possess deep knowledge of SystemVerilog, UVM, and DisplayPort verification, along with strong debugging and problem-solving capabilities.
Requirements
Key Responsibilities
Lead end-to-end verification activities for complex digital IPs, subsystems, and SoC designs
Develop comprehensive verification plans based on design specifications and functional requirements
Build scalable, reusable, and modular verification environments using SystemVerilog and UVM
Create constrained-random testbenches, assertions, scoreboards, functional coverage models, and verification components
Verify DisplayPort IPs and interfaces across multiple protocol versions and ensure compliance with industry standards
Collaborate closely with design, architecture, firmware, validation, and physical design teams throughout the development lifecycle
Perform simulation, debugging, root cause analysis, and issue resolution for functional failures
Drive coverage closure by monitoring functional, code, and assertion coverage metrics
Participate in design reviews, specification analysis, and architecture discussions to improve design quality and testability
Develop automation scripts to improve verification productivity and regression efficiency
Analyze protocol compliance, timing behavior, corner cases, and system-level interactions
Mentor junior verification engineers and provide technical guidance on verification best practices
Support post-silicon validation teams in debugging and resolving silicon issues when required
Required Qualifications
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related discipline
7-18 years of hands-on experience in Design Verification for ASIC, FPGA, or SoC development
Strong expertise in digital design verification methodologies and industry-standard verification flows
Excellent analytical, debugging, and communication skills
Experience leading verification teams or owning verification deliverables for complex projects is highly preferred
Must-Have Skills
Strong expertise in SystemVerilog for developing advanced verification environments
Extensive experience with UVM (Universal Verification Methodology) including reusable verification components, sequences, agents, scoreboards, and functional coverage
Hands-on experience verifying DisplayPort protocols and related interfaces
Expertise in constrained-random verification techniques and assertion-based verification
Experience with simulation, waveform debugging, regression management, and coverage-driven verification
Strong understanding of digital logic design, computer architecture, and hardware verification concepts
Experience with protocol verification, functional coverage, code coverage, and coverage closure
Familiarity with industry-standard EDA simulation and debugging tools
Good-to-Have Skills
Experience with additional high-speed protocols such as PCIe, USB, HDMI, MIPI, Ethernet, or DDR
Knowledge of scripting languages such as Python, Perl, Shell, or TCL for automation
Exposure to Formal Verification methodologies
Experience with emulation, FPGA prototyping, or hardware acceleration platforms
Understanding of low-power verification methodologies including UPF/CPF
Familiarity with CI/CD workflows for verification automation
Knowledge of SoC integration, AMBA protocols (AXI, AHB, APB), and embedded systems
Experience supporting post-silicon validation and debug activities
Show more Show less