VI
Lead ASIC DFT Staff Engineer
Accepting applicationsValue Innovation Labs · United States
Contract Mid_senior ASICATPGBoundary ScanCadenceDFT
Posted
20h ago
Category
Test
Experience
Mid_senior
Country
United States
🚨 HIRING | Lead ASIC DFT Staff Engineer (10 Years)
📍 Location: Remote – Must be aligned with PST Time Zone
🇺🇸 Visa: Any Visa
We are seeking a highly experienced Lead ASIC DFT Staff Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.
The ideal candidate will have strong hands-on experience across Scan, ATPG, MBIST/LBIST, DFT timing, JTAG, Boundary Scan, diagnosis, pattern retargeting, and post-silicon validation.
🔑 KEY SKILLS
SCAN | ATPG | MBIST | Timing Simulations | SDF | SDC | PSV | Diagnosis | Pattern Retargeting | Pattern Porting | DRCs | TetraMAX | DFTMAX
🔹 EXPERIENCE
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
🔹 KEY RESPONSIBILITIES
• Lead DFT architecture, implementation, verification, and sign-off for complex ASIC/SoC designs
• Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows
• Own MBIST/LBIST integration, implementation, verification, and debug
• Perform DFT failure analysis, root-cause investigation, and fault coverage closure
• Develop and validate DFT SDC constraints, timing checks, and DFT-specific timing analysis
• Collaborate with RTL, Verification, Physical Design, STA, and Silicon Validation teams
• Support ATPG pattern generation, ATPG simulations, DRC analysis, coverage analysis, diagnosis, and debug
• Work with JTAG, Boundary Scan, iJTAG, SSN, and IP-level DFT integration
• Review RTL, synthesis, LEC, and physical design impacts on DFT implementation
• Act as a technical escalation point for advanced DFT and post-silicon debug issues
• Mentor junior and mid-level DFT engineers
• Develop automation using TCL, PERL, or Python
⭐ REQUIRED SKILLS & QUALIFICATIONS
• 10+ years of hands-on ASIC DFT experience
• Strong end-to-end DFT ownership
• Strong understanding of DFT fundamentals, fault models, test techniques, and coverage
• Deep expertise in:
Scan
ATPG
MBIST
LBIST
JTAG
Boundary Scan
Silicon Debug
• Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
• Proven experience with scan insertion, ATPG setup, simulation, debug, and DRC analysis
• MBIST implementation and verification experience; SMS experience preferred
• Scan architecture and scan chain stitching experience
• Tessent/SSN experience preferred
• Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
• Proven post-silicon debug and silicon bring-up experience
• Experience with large SoC designs, hierarchical DFT flows, and multi-domain integration
• Strong communication skills
• Ability to work independently with minimal ramp-up
⭐ PREFERRED EXPERIENCE
• MBIST post-silicon validation
• ATPG simulations and fault coverage debug
• DFT RTL / DFD / DFT verification
• IP-level DFT integration
• DFT SDC creation and timing closure support
• Boundary Scan, iJTAG, and SSN
• Design-for-Debug methodologies
• TCL/PERL scripting for DFT automation and debug
• Experience across multiple ASIC technology nodes
• Complex semiconductor product development cycles
• Yield learning, diagnosis, and manufacturing test optimization
🔥 CORE TECHNOLOGIES
SCAN | ATPG | MBIST | LBIST | Synopsys SMS | TetraMAX | DFTMAX | Tessent | DFT | SDF | SDC | PSV | Timing Simulation | Pattern Retargeting | Pattern Porting | DRC | Diagnosis | JTAG | Boundary Scan | iJTAG | SSN | RTL | Synthesis | LEC | Silicon Bring-Up | Post-Silicon Debug | TCL | PERL | Python
🎯 IDEAL CANDIDATE
The ideal candidate is a senior/lead-level ASIC DFT engineer with strong end-to-end ownership who can independently drive DFT architecture, implementation, verification, ATPG, debug, coverage closure, and post-silicon validation for complex ASIC/SoC designs.
📩 Interested candidates: Please send your updated resume highlighting your ASIC DFT, Scan, ATPG, MBIST, TetraMAX, DFTMAX, SDF/SDC, Diagnosis, and Silicon Debug experience.
Please include:
✅ Current Location
✅ Visa Status
✅ Total DFT Experience
✅ ASIC/SoC Experience
✅ Key DFT Tools
✅ Availability
✅ Rate
✅ PST Time-Zone Alignment
#Hiring #NowHiring #ASIC #DFT #ASICDFT #DFTEngineer #LeadEngineer #StaffEngineer #ATPG #MBIST #Scan #LBIST #TetraMAX #DFTMAX #Tessent #Synopsys #Cadence #SiemensEDA #SoC #SiliconValidation #PostSilicon #Semiconductor #RemoteJobs #C2C #ContractJobs
Show more Show less
📍 Location: Remote – Must be aligned with PST Time Zone
🇺🇸 Visa: Any Visa
We are seeking a highly experienced Lead ASIC DFT Staff Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.
The ideal candidate will have strong hands-on experience across Scan, ATPG, MBIST/LBIST, DFT timing, JTAG, Boundary Scan, diagnosis, pattern retargeting, and post-silicon validation.
🔑 KEY SKILLS
SCAN | ATPG | MBIST | Timing Simulations | SDF | SDC | PSV | Diagnosis | Pattern Retargeting | Pattern Porting | DRCs | TetraMAX | DFTMAX
🔹 EXPERIENCE
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
🔹 KEY RESPONSIBILITIES
• Lead DFT architecture, implementation, verification, and sign-off for complex ASIC/SoC designs
• Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows
• Own MBIST/LBIST integration, implementation, verification, and debug
• Perform DFT failure analysis, root-cause investigation, and fault coverage closure
• Develop and validate DFT SDC constraints, timing checks, and DFT-specific timing analysis
• Collaborate with RTL, Verification, Physical Design, STA, and Silicon Validation teams
• Support ATPG pattern generation, ATPG simulations, DRC analysis, coverage analysis, diagnosis, and debug
• Work with JTAG, Boundary Scan, iJTAG, SSN, and IP-level DFT integration
• Review RTL, synthesis, LEC, and physical design impacts on DFT implementation
• Act as a technical escalation point for advanced DFT and post-silicon debug issues
• Mentor junior and mid-level DFT engineers
• Develop automation using TCL, PERL, or Python
⭐ REQUIRED SKILLS & QUALIFICATIONS
• 10+ years of hands-on ASIC DFT experience
• Strong end-to-end DFT ownership
• Strong understanding of DFT fundamentals, fault models, test techniques, and coverage
• Deep expertise in:
Scan
ATPG
MBIST
LBIST
JTAG
Boundary Scan
Silicon Debug
• Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
• Proven experience with scan insertion, ATPG setup, simulation, debug, and DRC analysis
• MBIST implementation and verification experience; SMS experience preferred
• Scan architecture and scan chain stitching experience
• Tessent/SSN experience preferred
• Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
• Proven post-silicon debug and silicon bring-up experience
• Experience with large SoC designs, hierarchical DFT flows, and multi-domain integration
• Strong communication skills
• Ability to work independently with minimal ramp-up
⭐ PREFERRED EXPERIENCE
• MBIST post-silicon validation
• ATPG simulations and fault coverage debug
• DFT RTL / DFD / DFT verification
• IP-level DFT integration
• DFT SDC creation and timing closure support
• Boundary Scan, iJTAG, and SSN
• Design-for-Debug methodologies
• TCL/PERL scripting for DFT automation and debug
• Experience across multiple ASIC technology nodes
• Complex semiconductor product development cycles
• Yield learning, diagnosis, and manufacturing test optimization
🔥 CORE TECHNOLOGIES
SCAN | ATPG | MBIST | LBIST | Synopsys SMS | TetraMAX | DFTMAX | Tessent | DFT | SDF | SDC | PSV | Timing Simulation | Pattern Retargeting | Pattern Porting | DRC | Diagnosis | JTAG | Boundary Scan | iJTAG | SSN | RTL | Synthesis | LEC | Silicon Bring-Up | Post-Silicon Debug | TCL | PERL | Python
🎯 IDEAL CANDIDATE
The ideal candidate is a senior/lead-level ASIC DFT engineer with strong end-to-end ownership who can independently drive DFT architecture, implementation, verification, ATPG, debug, coverage closure, and post-silicon validation for complex ASIC/SoC designs.
📩 Interested candidates: Please send your updated resume highlighting your ASIC DFT, Scan, ATPG, MBIST, TetraMAX, DFTMAX, SDF/SDC, Diagnosis, and Silicon Debug experience.
Please include:
✅ Current Location
✅ Visa Status
✅ Total DFT Experience
✅ ASIC/SoC Experience
✅ Key DFT Tools
✅ Availability
✅ Rate
✅ PST Time-Zone Alignment
#Hiring #NowHiring #ASIC #DFT #ASICDFT #DFTEngineer #LeadEngineer #StaffEngineer #ATPG #MBIST #Scan #LBIST #TetraMAX #DFTMAX #Tessent #Synopsys #Cadence #SiemensEDA #SoC #SiliconValidation #PostSilicon #Semiconductor #RemoteJobs #C2C #ContractJobs
Show more Show less