JV
Lead ASIC DFT Engineer
Accepting applicationsJobs via Dice · San Jose, CA
Full-Time Principal ASICATPGBISTCadenceDFT
Posted
22 Apr
Category
Test
Experience
Principal
Country
United States
Dice is the leading career destination for tech experts at every stage of their careers. Our client, TechSpace Solutions Inc., is seeking the following. Apply via Dice today!
Job Title: Lead ASIC DFT Engineer
Location: San Jose, CA - Must Be Able To Go In Office Once Or Twice A Month
Duration: Long term
Experience Required:
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
Key Skills Required:
Strong hands-on ASIC DFT experience with end-to-end ownership
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
MBIST implementation and verification; SMS experience preferred
Tessent/SSN experience preferred
Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
Post-silicon debug and silicon bring-up experience
TCL, PERL, or Python scripting experience is highly preferred
Show more Show less
Job Title: Lead ASIC DFT Engineer
Location: San Jose, CA - Must Be Able To Go In Office Once Or Twice A Month
Duration: Long term
Experience Required:
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
Key Skills Required:
Strong hands-on ASIC DFT experience with end-to-end ownership
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
MBIST implementation and verification; SMS experience preferred
Tessent/SSN experience preferred
Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
Post-silicon debug and silicon bring-up experience
TCL, PERL, or Python scripting experience is highly preferred
Show more Show less