Lead ASIC DFT Engineer

Lead ASIC DFT Engineer
Location: Remote (Must work PST hours)
Experience: 10+ Years in ASIC DFT Engineering

We are seeking a Lead ASIC DFT Engineer with 10+ years of experience in Design-for-Test (DFT) for complex ASIC and SoC designs. The ideal candidate will have strong expertise in Scan, ATPG, MBIST/LBIST, JTAG, Boundary Scan, Timing Simulations, SDF, SDC, Silicon Debug, and Post-Silicon Validation. Experience with Synopsys DFTMax, TetraMAX, Tessent, SSN, Pattern Retargeting/Porting, Diagnosis, and DFT Sign-off is required.
The role involves leading DFT architecture, implementation, verification, ATPG pattern generation, fault coverage closure, silicon bring-up, and cross-functional debug efforts. Strong scripting skills in TCL, Perl, or Python and experience with large SoC designs are highly preferred.
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