OG
Lead ASIC Design Engineer - Memory Controllers
Accepting applicationsOho Group · San Francisco Bay Area
Full-Time Principal ASICRTLSoCSystemVerilog
Posted
1d ago
Category
Design
Experience
Principal
Country
United States
Lead ASIC Designer - Memory Controllers
A well-backed stealth startup working on next-generation silicon is looking for a lead-level engineer to take ownership of a complex memory subsystem, working across architecture, RTL design and silicon implementation.
This is a hands-on role for someone who enjoys solving challenging hardware problems and working across multiple areas of chip development.
The Role
Own memory subsystem architecture and microarchitecture through implementation.
Design and develop high-performance memory controller logic.
Write and review high-quality SystemVerilog RTL.
Optimise designs across performance, power and area.
Work closely with verification and physical design teams to achieve implementation goals.
Contribute to timing, synthesis, CDC and design-quality activities.
Help debug and resolve complex hardware issues throughout the development cycle.
Provide technical guidance and mentorship to other engineers.
What We're Looking For
15+ years of experience in memory controller or memory subsystem design.
Strong hands-on experience with ASIC/SoC RTL development.
Deep understanding of memory architecture and controller design.
Experience with DRAM or other high-performance memory technologies.
Strong SystemVerilog skills.
Experience taking complex designs through the ASIC development lifecycle.
Strong understanding of performance, power and area trade-offs.
Comfortable working cross-functionally with architecture, verification and physical design teams.
Proven ability to take ownership of technically complex projects.
If you're looking to take ownership in an early-stage project, please apply today.
Show more Show less
A well-backed stealth startup working on next-generation silicon is looking for a lead-level engineer to take ownership of a complex memory subsystem, working across architecture, RTL design and silicon implementation.
This is a hands-on role for someone who enjoys solving challenging hardware problems and working across multiple areas of chip development.
The Role
Own memory subsystem architecture and microarchitecture through implementation.
Design and develop high-performance memory controller logic.
Write and review high-quality SystemVerilog RTL.
Optimise designs across performance, power and area.
Work closely with verification and physical design teams to achieve implementation goals.
Contribute to timing, synthesis, CDC and design-quality activities.
Help debug and resolve complex hardware issues throughout the development cycle.
Provide technical guidance and mentorship to other engineers.
What We're Looking For
15+ years of experience in memory controller or memory subsystem design.
Strong hands-on experience with ASIC/SoC RTL development.
Deep understanding of memory architecture and controller design.
Experience with DRAM or other high-performance memory technologies.
Strong SystemVerilog skills.
Experience taking complex designs through the ASIC development lifecycle.
Strong understanding of performance, power and area trade-offs.
Comfortable working cross-functionally with architecture, verification and physical design teams.
Proven ability to take ownership of technically complex projects.
If you're looking to take ownership in an early-stage project, please apply today.
Show more Show less