RI
Lead Application Engineer (Trainer in VLSI)
Accepting applicationsRamaiah Institute for Advanced Skills and Technology (RIASAT) · Bengaluru South, Karnataka, India
Full-Time Mid_senior CadenceGenusRISC-VRTLSynopsys
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Verification
Experience
Mid_senior
Country
India
Experience and Qualification:
Qualification: B.E./B.Tech
Experience: 5 + Years (Industry Experience is an added advantage)
At Ramaiah Institute for Advanced Skills and Technology (RAF), Talent is at the core of all our People Strategy. The wide wealth of talent includes Research Scholars, Faculty members, Trainers, Deep Tech Engineers, Technologists, Corporate Leaders, Institutional administrators and best in class functional specialists.
To be a part of this phenomenal journey of transformation from better to best, do apply for the following open position at Ramaiah Institute for Advanced Skills and Technology (RAF) by mailing your Resume to talent@ramaiahacademy.com
Job Description:
Ramaiah Skills Academy is seeking a technical leader to serve as the Lead Application Engineering of VLSI Design. In this role, the incumbent will spearhead the vision, curriculum design and delivery of advanced training programs in RTL Design, Functional Verification, and Digital System Architectures. The incumbent will lead a team of Application Engineers and trainers, establishing industry-standard methodologies to bridge the gap between academia and corporate semiconductor engineering.
The ideal candidate possesses comprehensive, hands-on mastery of frontend VLSI flows, advanced verification methodologies (UVM, SVA), and chip synthesis/timing analysis, alongside the leadership acumen to mentor next-generation VLSI professionals and corporate learners.
Roles & Responsibilities:
Strategic Leadership & Curriculum Architecture: Define the technical roadmap for the VLSI division. Design, audit, and continuously upgrade high-quality, industry-aligned curricula, assignments, and advanced project frameworks covering Digital Design through to STA.
Program Delivery & Master Instruction: Deliver high-impact, advanced classroom and online training sessions on complex topics including SystemVerilog OOP, UVM testbench architectures, constrained random verification, and advanced Static Timing Analysis (STA).
Team & Lab Management: Supervise and mentor a team of Application Engineers and trainers. Oversee the setup, deployment, and maintenance of industry-grade EDA tool flows within the Academy’s laboratories.
Project Mentorship & Evaluation: Architecture and guide real-time, tape-out quality capstone projects (e.g., RISC-V processors, high-speed interconnects, or hardware accelerators). Establish rigorous evaluation standards and interview preparation strategies.
Industry Collaboration: Foster deep relationships with semiconductor companies, design houses, and EDA vendors to align training paradigms with contemporary industry constraints and placement demands.
Skill Requirements:
Core Technical Expertise: Authoritative knowledge of Verilog, SystemVerilog, advanced RTL design principles (FSM design, clock domain crossing, low-power design), and advanced computer architecture.
Verification Mastery: Deep-dive expertise in the Universal Verification Methodology (UVM), SystemVerilog Assertions (SVA), Functional Coverage modelling, and building complex, reusable constrained-random verification environments.
Implementation & Sign-off: Thorough understanding of RTL Synthesis, Synopsys Design Constraints (SDC) generation, and Static Timing Analysis (STA) closure methodologies.
EDA Tool Suite Proficiency: Expert-level command over industry-standard EDA tools from Cadence or Synopsys (e.g., VCS, Verdi, Design Compiler, PrimeTime, Spyglass, Formality, Xcelium, or Genus).
Soft Skills & Pedagogy: Exceptional communication, lecturing, and leadership skills with a passion for knowledge transfer, talent development, and technical writing.
Show more Show less
Qualification: B.E./B.Tech
Experience: 5 + Years (Industry Experience is an added advantage)
At Ramaiah Institute for Advanced Skills and Technology (RAF), Talent is at the core of all our People Strategy. The wide wealth of talent includes Research Scholars, Faculty members, Trainers, Deep Tech Engineers, Technologists, Corporate Leaders, Institutional administrators and best in class functional specialists.
To be a part of this phenomenal journey of transformation from better to best, do apply for the following open position at Ramaiah Institute for Advanced Skills and Technology (RAF) by mailing your Resume to talent@ramaiahacademy.com
Job Description:
Ramaiah Skills Academy is seeking a technical leader to serve as the Lead Application Engineering of VLSI Design. In this role, the incumbent will spearhead the vision, curriculum design and delivery of advanced training programs in RTL Design, Functional Verification, and Digital System Architectures. The incumbent will lead a team of Application Engineers and trainers, establishing industry-standard methodologies to bridge the gap between academia and corporate semiconductor engineering.
The ideal candidate possesses comprehensive, hands-on mastery of frontend VLSI flows, advanced verification methodologies (UVM, SVA), and chip synthesis/timing analysis, alongside the leadership acumen to mentor next-generation VLSI professionals and corporate learners.
Roles & Responsibilities:
Strategic Leadership & Curriculum Architecture: Define the technical roadmap for the VLSI division. Design, audit, and continuously upgrade high-quality, industry-aligned curricula, assignments, and advanced project frameworks covering Digital Design through to STA.
Program Delivery & Master Instruction: Deliver high-impact, advanced classroom and online training sessions on complex topics including SystemVerilog OOP, UVM testbench architectures, constrained random verification, and advanced Static Timing Analysis (STA).
Team & Lab Management: Supervise and mentor a team of Application Engineers and trainers. Oversee the setup, deployment, and maintenance of industry-grade EDA tool flows within the Academy’s laboratories.
Project Mentorship & Evaluation: Architecture and guide real-time, tape-out quality capstone projects (e.g., RISC-V processors, high-speed interconnects, or hardware accelerators). Establish rigorous evaluation standards and interview preparation strategies.
Industry Collaboration: Foster deep relationships with semiconductor companies, design houses, and EDA vendors to align training paradigms with contemporary industry constraints and placement demands.
Skill Requirements:
Core Technical Expertise: Authoritative knowledge of Verilog, SystemVerilog, advanced RTL design principles (FSM design, clock domain crossing, low-power design), and advanced computer architecture.
Verification Mastery: Deep-dive expertise in the Universal Verification Methodology (UVM), SystemVerilog Assertions (SVA), Functional Coverage modelling, and building complex, reusable constrained-random verification environments.
Implementation & Sign-off: Thorough understanding of RTL Synthesis, Synopsys Design Constraints (SDC) generation, and Static Timing Analysis (STA) closure methodologies.
EDA Tool Suite Proficiency: Expert-level command over industry-standard EDA tools from Cadence or Synopsys (e.g., VCS, Verdi, Design Compiler, PrimeTime, Spyglass, Formality, Xcelium, or Genus).
Soft Skills & Pedagogy: Exceptional communication, lecturing, and leadership skills with a passion for knowledge transfer, talent development, and technical writing.
Show more Show less