LT
Lead Analog Layout Engineer
Accepting applicationsLeadSoc Technologies Pvt Ltd · Hyderabad, Telangana, India
Full-Time Mid_senior AnalogCadenceCalibreMentorMixed-Signal
Estimated market salary
₹46-83 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
India
Lead Analog Layout Engineer
Location: Hyderabad, India
Experience: 4–12 Years
Role
Join a high-performance silicon team developing next-generation Analog & Mixed-Signal IPs on TSMC 3nm/2nm technologies. You will own full-custom layout implementation, physical verification, and electrical closure for complex analog macros powering advanced SoCs.
What You'll Do
Design full-custom analog and mixed-signal layouts for PLL, Bandgap, ADC, DAC, LDO, and related IPs.
Drive layout execution from floorplanning to GDSII sign-off.
Perform DRC, LVS, ERC, and physical verification using Calibre.
Deliver chip-level integration, parasitic optimization, and electrical closure.
Optimize layouts for matching, symmetry, reliability, EM/IR, and manufacturability.
Collaborate closely with circuit design, CAD, and technology teams.
What We're Looking For
6–12 years of experience in Custom Analog Layout.
Strong expertise in Cadence Virtuoso and Mentor Calibre.
Hands-on experience with PLL, Bandgap, ADC, DAC, or similar analog IPs.
Deep understanding of layout-dependent effects (LDE), matching, parasitics, and reliability.
Experience with advanced nodes (TSMC 3nm/2nm preferred) and chip-level integration.
Strong debugging, ownership, and problem-solving skills.
Qualifications
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related field.
Build the analog foundation for tomorrow's compute platforms on the world's most advanced process technologies.
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Location: Hyderabad, India
Experience: 4–12 Years
Role
Join a high-performance silicon team developing next-generation Analog & Mixed-Signal IPs on TSMC 3nm/2nm technologies. You will own full-custom layout implementation, physical verification, and electrical closure for complex analog macros powering advanced SoCs.
What You'll Do
Design full-custom analog and mixed-signal layouts for PLL, Bandgap, ADC, DAC, LDO, and related IPs.
Drive layout execution from floorplanning to GDSII sign-off.
Perform DRC, LVS, ERC, and physical verification using Calibre.
Deliver chip-level integration, parasitic optimization, and electrical closure.
Optimize layouts for matching, symmetry, reliability, EM/IR, and manufacturability.
Collaborate closely with circuit design, CAD, and technology teams.
What We're Looking For
6–12 years of experience in Custom Analog Layout.
Strong expertise in Cadence Virtuoso and Mentor Calibre.
Hands-on experience with PLL, Bandgap, ADC, DAC, or similar analog IPs.
Deep understanding of layout-dependent effects (LDE), matching, parasitics, and reliability.
Experience with advanced nodes (TSMC 3nm/2nm preferred) and chip-level integration.
Strong debugging, ownership, and problem-solving skills.
Qualifications
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related field.
Build the analog foundation for tomorrow's compute platforms on the world's most advanced process technologies.
Show more Show less