IR
Layout Design Engineer
Accepting applicationsIC Resources · San Francisco Bay Area
Full-Time Mid_senior AnalogCMOSCadenceCalibreMixed-Signal
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
CMOS Layout Design Engineer – High-Speed Logic & Photonics
A well-funded deep-tech semiconductor company is developing next-generation computing and connectivity technologies that combine advanced CMOS design with integrated photonics.
The organization is building highly complex silicon platforms designed to overcome performance and efficiency limitations in modern computing systems. Their multidisciplinary engineering teams work across IC design, photonics, packaging, and systems engineering to develop cutting-edge hardware for emerging compute-intensive applications.
We are seeking a CMOS Layout Design Engineer to join a growing IC design team focused on custom layout development for high-speed analog, mixed-signal, and photonic integrated circuits.
Role Overview
This role is responsible for full-custom CMOS layout development from block-level implementation through top-level integration and tape-out.
The engineer will work closely with circuit designers to optimize layouts for performance, noise, reliability, and manufacturability while supporting advanced CMOS technologies and monolithically integrated photonic components.
This position requires strong expertise in analog and mixed-signal layout techniques, physical verification, and tape-out execution within advanced semiconductor processes.
Key Responsibilities
Develop full-custom layout for analog, mixed-signal, and high-speed circuit blocks
Perform block-level and top-level physical integration activities
Apply advanced layout methodologies including device matching, common-centroid placement, symmetry techniques, shielding, and critical-net routing
Optimize layouts to minimize parasitic effects and maximize circuit performance
Support integration of photonic structures within CMOS process technologies
Participate in floorplanning, routing strategy, and physical design reviews
Implement ESD structures, I/O ring integration, and padframe layouts
Execute physical verification flows including DRC, LVS, parasitic extraction, and tape-out signoff
Collaborate closely with design engineers to resolve layout-driven performance issues
Support engineering change orders and late-stage design modifications
Required Qualifications
Bachelor's degree in Electrical Engineering or a related discipline
5+ years of experience in custom CMOS layout design
Strong experience with analog and mixed-signal layout techniques
Expertise in device matching, symmetry, common-centroid structures, and parasitic-aware layout practices
Experience with advanced CMOS process technologies
Proficiency with Cadence Virtuoso Layout XL/GXL
Experience with physical verification tools such as Calibre or equivalent
Familiarity with parasitic extraction and tape-out methodologies
Experience implementing ESD structures and pad frame integration
Preferred Qualifications
Experience with high-speed logic or mixed-signal circuits
Exposure to photonic integrated circuits or silicon photonics technologies
Knowledge of reliability considerations including electromigration, IR drop, and latch-up prevention
Experience with SKILL, Python, or layout automation methodologies
Prior experience supporting advanced-node tape-outs
Compensation & Benefits
Competitive base salary ($190K-$210K) and bonus opportunity
Comprehensive medical, dental, and vision coverage
Retirement savings program
Generous paid time off
Opportunity to work on industry-leading semiconductor and photonics technologies
Collaborative environment with strong technical ownership and career growth opportunities
CMOS Layout Engineer, Custom Layout Engineer, Analog Layout Engineer, Mixed-Signal Layout Engineer, Physical Layout Engineer, IC Layout Engineer, Custom IC Layout, Cadence Virtuoso, Calibre, DRC, LVS, PEX, Tape-Out, Analog IC Design, Mixed-Signal IC Design, Semiconductor Design, Silicon Photonics, Photonic Integrated Circuits, High-Speed Logic
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A well-funded deep-tech semiconductor company is developing next-generation computing and connectivity technologies that combine advanced CMOS design with integrated photonics.
The organization is building highly complex silicon platforms designed to overcome performance and efficiency limitations in modern computing systems. Their multidisciplinary engineering teams work across IC design, photonics, packaging, and systems engineering to develop cutting-edge hardware for emerging compute-intensive applications.
We are seeking a CMOS Layout Design Engineer to join a growing IC design team focused on custom layout development for high-speed analog, mixed-signal, and photonic integrated circuits.
Role Overview
This role is responsible for full-custom CMOS layout development from block-level implementation through top-level integration and tape-out.
The engineer will work closely with circuit designers to optimize layouts for performance, noise, reliability, and manufacturability while supporting advanced CMOS technologies and monolithically integrated photonic components.
This position requires strong expertise in analog and mixed-signal layout techniques, physical verification, and tape-out execution within advanced semiconductor processes.
Key Responsibilities
Develop full-custom layout for analog, mixed-signal, and high-speed circuit blocks
Perform block-level and top-level physical integration activities
Apply advanced layout methodologies including device matching, common-centroid placement, symmetry techniques, shielding, and critical-net routing
Optimize layouts to minimize parasitic effects and maximize circuit performance
Support integration of photonic structures within CMOS process technologies
Participate in floorplanning, routing strategy, and physical design reviews
Implement ESD structures, I/O ring integration, and padframe layouts
Execute physical verification flows including DRC, LVS, parasitic extraction, and tape-out signoff
Collaborate closely with design engineers to resolve layout-driven performance issues
Support engineering change orders and late-stage design modifications
Required Qualifications
Bachelor's degree in Electrical Engineering or a related discipline
5+ years of experience in custom CMOS layout design
Strong experience with analog and mixed-signal layout techniques
Expertise in device matching, symmetry, common-centroid structures, and parasitic-aware layout practices
Experience with advanced CMOS process technologies
Proficiency with Cadence Virtuoso Layout XL/GXL
Experience with physical verification tools such as Calibre or equivalent
Familiarity with parasitic extraction and tape-out methodologies
Experience implementing ESD structures and pad frame integration
Preferred Qualifications
Experience with high-speed logic or mixed-signal circuits
Exposure to photonic integrated circuits or silicon photonics technologies
Knowledge of reliability considerations including electromigration, IR drop, and latch-up prevention
Experience with SKILL, Python, or layout automation methodologies
Prior experience supporting advanced-node tape-outs
Compensation & Benefits
Competitive base salary ($190K-$210K) and bonus opportunity
Comprehensive medical, dental, and vision coverage
Retirement savings program
Generous paid time off
Opportunity to work on industry-leading semiconductor and photonics technologies
Collaborative environment with strong technical ownership and career growth opportunities
CMOS Layout Engineer, Custom Layout Engineer, Analog Layout Engineer, Mixed-Signal Layout Engineer, Physical Layout Engineer, IC Layout Engineer, Custom IC Layout, Cadence Virtuoso, Calibre, DRC, LVS, PEX, Tape-Out, Analog IC Design, Mixed-Signal IC Design, Semiconductor Design, Silicon Photonics, Photonic Integrated Circuits, High-Speed Logic
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