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Job Title: Senior Physical Design / STA Engineer - W2
Accepting applicationsJobs via Dice · Carmel, CA
Full-Time Senior ASICDFTRTLSoCate
Posted
6h ago
Category
Design
Experience
Senior
Country
United States
Dice is the leading career destination for tech experts at every stage of their careers. Our client, MASH Pro Tech, is seeking the following. Apply via Dice today!
Job Title: Senior Physical Design / STA Engineer
Location: Bay Area, CA / Austin, TX - CA 1st preference
Employment Type: Long-Term Contract (W2 Only)
Position Summary
We are seeking a Senior Physical Design / STA Engineer with strong hands-on experience in physical design and static timing analysis for advanced semiconductor projects. The ideal candidate will have expertise in timing closure, synthesis, place & route, and signoff activities for high-performance ASIC/SoC designs.
Responsibilities
Perform full-chip and block-level physical design implementation.
Execute Static Timing Analysis (STA) and timing closure activities.
Work on floorplanning, placement, clock tree synthesis (CTS), routing, and signoff.
Analyze and resolve setup/hold timing violations.
Collaborate with RTL, DFT, and backend design teams.
Support low-power and high-performance design optimization.
Participate in design reviews and debugging activities.
Ensure designs meet power, performance, and area (PPA) targets.
Required Skills
7+ years of experience in Physical Design and STA.
Strong expertise in timing closure and signoff flows.
Experience with industry-standard EDA tools for STA and physical design.
Knowledge of synthesis, floorplanning, CTS, routing, and ECO flows.
Strong understanding of ASIC/SoC design methodologies.
Experience with advanced technology nodes is preferred.
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Job Title: Senior Physical Design / STA Engineer
Location: Bay Area, CA / Austin, TX - CA 1st preference
Employment Type: Long-Term Contract (W2 Only)
Position Summary
We are seeking a Senior Physical Design / STA Engineer with strong hands-on experience in physical design and static timing analysis for advanced semiconductor projects. The ideal candidate will have expertise in timing closure, synthesis, place & route, and signoff activities for high-performance ASIC/SoC designs.
Responsibilities
Perform full-chip and block-level physical design implementation.
Execute Static Timing Analysis (STA) and timing closure activities.
Work on floorplanning, placement, clock tree synthesis (CTS), routing, and signoff.
Analyze and resolve setup/hold timing violations.
Collaborate with RTL, DFT, and backend design teams.
Support low-power and high-performance design optimization.
Participate in design reviews and debugging activities.
Ensure designs meet power, performance, and area (PPA) targets.
Required Skills
7+ years of experience in Physical Design and STA.
Strong expertise in timing closure and signoff flows.
Experience with industry-standard EDA tools for STA and physical design.
Knowledge of synthesis, floorplanning, CTS, routing, and ECO flows.
Strong understanding of ASIC/SoC design methodologies.
Experience with advanced technology nodes is preferred.
Show more Show less