TM
Job Opportunity For Lead Design Verification Role
Accepting applicationsTech Mahindra · Karnataka, India
Full-Time Mid_senior UVMVerilog
Estimated market salary
₹8-14 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
5d ago
Category
Verification
Experience
Mid_senior
Country
India
Hi everyone,
We are looking For Design Verification engineer with UCIe & HSIO (High Speed IO) Protocol verification
Required Skills:
UCIe & HSIO (High Speed IO) Protocol verification
System Verilog, Verilog
Simulation UVM
High Speed Protocols
Interested can share the resume on this mail id
Preeti.Rajput@TechMahindra.com
Show more Show less
We are looking For Design Verification engineer with UCIe & HSIO (High Speed IO) Protocol verification
Required Skills:
UCIe & HSIO (High Speed IO) Protocol verification
System Verilog, Verilog
Simulation UVM
High Speed Protocols
Interested can share the resume on this mail id
Preeti.Rajput@TechMahindra.com
Show more Show less